MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 345

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.3.4
Freescale Semiconductor
(Write Only
read always
0)
Reset
IICEN
TXAK
RSTA
Field
IICIE
MST
TX
7
6
5
4
3
2
W
R
IICEN
IIC Control Register (IICC1)
IIC Enable — The IICEN bit determines whether the IIC module is enabled.
0 IIC is not enabled.
1 IIC is enabled.
IIC Interrupt Enable — The IICIE bit determines whether an IIC interrupt is requested.
0 IIC interrupt request not enabled.
1 IIC interrupt request enabled.
Master Mode Select — When the MST bit is changed from a 0 to a 1, a START signal is generated on the bus
and master mode is selected. When this bit changes from a 1 to a 0 a STOP signal is generated and the mode
of operation changes from master to slave.
0 Slave mode.
1 Master mode.
Transmit Mode Select — The TX bit selects the direction of master and slave transfers. In master mode this bit
should be set according to the type of transfer required. Therefore, for address cycles, this bit will always be high.
When addressed as a slave this bit should be set by software according to the SRW bit in the status register.
0 Receive.
1 Transmit.
Transmit Acknowledge Enable — This bit specifies the value driven onto the SDA during data acknowledge
cycles for both master and slave receivers.
There are two conditions will effect NAK/ACK generation.
If FACK (fast NACK/ACK) is cleared,
0 An acknowledge signal will be sent out to the bus on the following receiving data byte.
1 No acknowledge signal response is sent to the bus on the following receiving data byte.
If FASK bit is set. no ACK or NACK is sent out after receiving one data byte until this TXAK bit is written
0 An acknowledge signal will be sent out to the bus on the current receiving data byte
1 No acknowledge signal response is sent to the bus on the current receiving data byte
Note: SCL is held to low until TXAK is written.
Repeat START — Writing a 1 to this bit will generate a repeated START condition provided it is the current
master. Attempting a repeat at the wrong time will result in loss of arbitration.
0 No repeat start detected in bus operation.
1 Repeat start generated.
0
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
= Unimplemented or Reserved
IICIE
0
6
Figure 15-4. IIC Control Register (IICC1)
Table 15-5. IICC1 Field Descriptions
MST
0
5
TX
0
4
Description
TXAK
3
0
RSTA
0
2
Inter-Integrated Circuit (IIC)
0
1
0
0
15-7