MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 181

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
7.7.5
This register includes read-only status flags to indicate the source of the most recent reset. When a debug
host forces reset by setting CSR2[BDFR], none of the status bits in SRS will be set. Writing any value to
this register address clears the COP watchdog timer without affecting the contents of this register. The reset
state of these bits depends on what caused the microcontroller to reset.
Freescale Semiconductor
Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits
corresponding to sources that are not active at the time of reset entry will be cleared.
reset:
POR:
LVWIE
other
LVD:
Field
Any
2–0
3
W
R
System Reset Status Register (SRS)
POR
Low-Voltage Warning Interrupt Enable. This bit enables hardware interrupt requests for LVWF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVWF is set.
Reserved, should be cleared.
1
u
0
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Not Recommended
LVDV:LVWV
Note
PIN
00
01
10
11
0
0
6
1
Table 7-8. LVD and LVW Trip Point Typical Values
Writing any value to SRS address clears COP watchdog timer.
Table 7-7. SPMSC3 Bit Field Descriptions
Figure 7-5. System Reset Status (SRS)
Note
COP
0
0
5
1
LVW Trip Point
V
V
V
V
LVWL
LVWL
LVWH
LVWH
Note
ILOP
0
0
4
= 2.15
= 2.15
= 2.6
= 2.6
1
Description
Note
ILAD
3
0
0
1
Resets, Interrupts, and General System Control
LVD Trip Point
V
V
LVDH
LVDL
0
2
0
0
0
= 1.84
= 2.33
LVD
1
1
0
1
0
0
0
0
0
7-15