MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 399

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.5.8
The seconds alarm register is used to configure the seconds setting of the alarm. The alarm setting can be
read or written anytime. This register is reset to default value on software reset. In BCD mode, all 8-bits
are used to indicate the time.
Bits 9 & 8 provide option to the MCU to perform correction on seconds counter to compensate for the leap
seconds. Write to these bits adds or subtracts 1 from the seconds counter and read returns zeros. MCU
should first read the INVAL bit of the IRTC_STATUS (bit 0) to determine that the counters are stable and
they can be incremented. The INVAL bit ensures that no operation is done at the boundary of a second
when counters change value. MCU should check the status of this bit both during reads and writes.
Freescale Semiconductor
ALM_SECONDS
Reset Value
Reset Value
DEC_S
INC_S
15–10
Field
IRTC_ALM_SEC
Field (bcd)
Field (bcd)
Field (bin)
Field (bin)
7–6
5–0
9
8
Bit Type
Bit Type
IRTC Seconds Alarm Register (IRTC_ALM_SEC)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Reserved bits. Not writeable. Read returns zeros.
This bit controls the increment of seconds counter incase the MCU wants to make corrections to the
seconds counter to compensate for the leap seconds or to perform fine trimming of time when needed.
Write to this bit has increments the seconds counter and then the bit gets cleared on next posedge.
This bit controls the decrement of seconds counter incase the MCU wants to make corrections to the
seconds counter to compensate for the leap seconds or to perform fine trimming of time when needed.
Write to this bit has decrements the seconds counter and then the bit gets cleared on next posedge.
Reserved bits in Binary mode. Read returns zeros. In BCD mode, these are used.
Alarm Seconds Value. Count: 0 – 59
Bit 15
rsvd
rsvd
Bit 7
—
—
Figure 17-9. IRTC Seconds Alarm Register (IRTC_ALM_SEC)
ALM_SECONDS (tens)
Bit 14
rsvd
rsvd
Bit 6
Table 17-9. IRTC_ALM_SEC Field Descriptions
—
—
Bit 13
rsvd
Bit 5
—
rw
0
Seconds Alarm Register
Bit 12
rsvd
Bit 4
—
rw
0
Description
ALM_SECONDS
Bit 11
rsvd
Bit 3
—
rw
0
ALM_SECONDS (units)
Bit 10
rsvd
Bit 2
—
rw
Independent Robust Real Time Clock (IRTC)
0
INC_S
INC_S
Bit 9
Bit 1
sclr
rw
0
0
DEC_S
DEC_S
Bit 8
Bit 0
sclr
Offset: 0x0E
rw
0
0
0x0E
0x0F
17-15