MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 572

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DRc[4:0]: 0x00 (CSR)
Version 1 ColdFire Debug (CF1_DEBUG)
26-8
Reset
Reset
BSTAT
31–28
23–20
BKPT
HALT
Field
TRG
FOF
HRL
27
26
25
24
19
W
W
R
R
31
15
0
0
0
Breakpoint status. Provides read-only status (from the BDM port only) information concerning hardware
breakpoints. BSTAT is cleared by a TDR write, by a CSR read when a level-2 breakpoint is triggered, or a level-1
breakpoint is triggered and the level-2 breakpoint is disabled.
The PSTB value that follows the PSTB entry of 0x1B is 0x20 + (2 × BSTAT).
0000 No breakpoints enabled
0001 Waiting for level-1 breakpoint
0010 Level-1 breakpoint triggered
0101 Waiting for level-2 breakpoint
0110 Level-2 breakpoint triggered
Fault-on-fault. Indicates a catastrophic halt occurred and forced entry into BDM. FOF is cleared by reset or when
CSR is read (from the BDM port only).
Hardware breakpoint trigger. Indicates a hardware breakpoint halted the processor core and forced entry into
BDM. Reset, the debug GO command, or reading CSR (from the BDM port only) clears TRG.
Processor halt. Indicates the processor executed a HALT and forced entry into BDM. Reset, the debug
command, or reading CSR (from the BDM port only) clears HALT.
Breakpoint assert. Indicates when either:
This forces the processor into a BDM halt. Reset, the debug
only) clears BKPT.
Hardware revision level. Indicates, from the BDM port only, the level of debug module functionality. An emulator
can use this information to identify the level of functionality supported.
0000 Revision A
0001 Revision B
0010 Revision C
0011 Revision D
1001 Revision B+ (The value used for this device)
1011 Revision D+
Reserved, must be cleared.
• The BKPT input was asserted,
• BDM BACKGROUND command received, or
• The PSTB halt on full condition, CSR2[PSTBH], sets.
TRC
30
14
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
0
0
BSTAT
29
13
0
0
0
28
12
0
0
Figure 26-3. Configuration/Status Register (CSR)
DDC
FOF
27
11
0
0
Table 26-5. CSR Field Descriptions
TRG HALT BKPT
UHE
26
10
0
0
25
0
0
9
BTB
24
0
0
8
Description
23
1
0
0
7
GO
NPL
22
0
0
6
command, or reading CSR (from the BDM port
HRL
IPI
21
0
0
5
SSM
20
1
4
0
Access: Supervisor write-only
19
0
0
0
0
3
Freescale Semiconductor
BKD
18
0
0
0
2
BDM read/write
FID
17
0
0
0
1
GO
DDH
IPW
16
0
0
0