MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 227

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

if extension word, bit [5] = 1, the MASK bit, then
Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For
auto-addressing modes of post-increment and pre-decrement, the updated An value calculation is also
shown.
Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue
implementations.
9.2.3
The accumulator register store 32-bits of the MAC operation result.
Freescale Semiconductor
MASK
Field
15–0
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
BDM: Read: 0xE6 (ACC)
if <ea> = (An)
if <ea> = (An)+
if <ea> =-(An)
if <ea> = (d16,An)
Reset
BDM: Read: 0xE5 (MASK)
W
R
Accumulator Register (ACC)
W
Write: 0xC6
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
R
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Write: 0xC5
Performs a simple AND with the operand address for MAC instructions.
15
1
oa
oa
An = (An + 4) & {0xFFFF, MASK}
oa
An = (An - 4) & {0xFFFF, MASK}
oa
14
1
=
=
= (An - 4) & {0xFFFF, MASK}
= (An + se_d16) & {0xFFFF0x, MASK}
An & {0xFFFF, MASK}
An
13
1
Figure 9-4. Accumulator Register (ACC)
12
1
Table 9-4. MASK Field Descriptions
Figure 9-3. Mask Register (MASK)
11
1
10
1
1
9
Accumulator
8
1
MASK
Description
1
7
1
6
1
5
1
4
8
Access: User read/write
1
3
7
Access: User read/write
Multiply-Accumulate Unit (MAC)
6
BDM read/write
1
2
5
BDM read/write
4
1
1
3
2
1
0
1
0
9-5