MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 422

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Independent Robust Real Time Clock (IRTC)
Vital Statistics:
Compensation Flow:
The operation starts in an IDLE state waiting for the firmware to enable compensation. Since the same
hardware logic is used for temperature and crystal compensation, the firmware should be able to provide
a value that takes into account correction for both temperature and crystal. When enabled, the
compensation cycles are added or removed till the compensation interval expires. On completion of the
compensation interval, the done bit is asserted to the CPU and if compensation is still enabled, the next
compensation cycle starts. Compensation state machine returns to IDLE state when compensation is
disabled by writing 0 to compensation interval. A newly programmed value is picked only when the
current compensation cycle has completed.
Figure 17-27
explained in subsequent pages.
Compensation Logic Hardware:
The compensation logic hardware comprises of a simple counter (irtc_osc_32k_div_counter) which
divides the 32 kHz clock down to 1 Hz by counting up till 32767. In order to add or remove pulses the start
point of the counter is shifted and the counter still counts up to 32767 to generate a balanced 1 Hz clock.
The state machine for this block controls the loading of correction value into the counter and ensures that
each compensation window is always aligned to the seconds boundary. Switching to newly programmed
compensation values is done when the compensation interval of current run is complete and CPU has not
17-38
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Compensation/Correction value: Compensation/Correction Value is a 2’s complement value with
which the IRTC oscillator clock is modified by either adding or removing pulses from it.
Compensation interval: compensation Interval is the duration in which the correction value is
applied. This is the time in which this block adds or removes pulses thereby ensuring that the
compensation interval is close to the interval obtained with an ideal 1 Hz clock.
Range of compensation Interval: 1 second to 255 seconds (0 disables compensation)
Range of compensation: –128 clocks to 127clocks (IRTC oscillator clocks)
Selection criteria: Compensation is done only when enabled by CPU. CPU can disable
compensation by programming a 0 compensation interval
shows the flow chart for the logical compensation flow of the state machine which has been
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 17-27. Compensation Control Flow
Freescale Semiconductor