MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 91

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.4.3.6
The FxCMD register is the flash command register. All FxCMD bits are readable and writable during a
command write sequence while bit 7 reads 0 and is not writable.
Freescale Semiconductor
FACCERR
x
FBLANK
FPVIOL
FCBEF
Reset
FCCF
Field
1–0
7
6
5
4
3
2
W
R
Command Buffer Empty Flag. The FCBEF flag indicates that the command buffer is empty so that a new
command write sequence can be started when performing burst programming. Writing a 0 to the FCBEF flag has
no effect on FCBEF. Writing a 0 to FCBEF after writing an aligned address to the flash array memory, but before
FCBEF is cleared, aborts a command write sequence and causes the FACCERR flag to be set. Writing a 0 to
FCBEF outside of a command write sequence does not set the FACCERR flag. Writing a 1 to this bit clears it.
0 Command buffers are full.
1 Command buffers are ready to accept a new command.
Command Complete Flag. The FCCF flag indicates that there are no more commands pending. The FCCF flag
is cleared when FCBEF is cleared and sets automatically upon completion of all active and pending commands.
The FCCF flag does not set when an active program command completes and a pending burst program
command is fetched from the command buffer. Writing to the FCCF flag has no effect on FCCF.
0 Command in progress.
1 All commands are completed.
Protection Violation Flag. The FPVIOL flag indicates an attempt was made to program or erase an address in
a protected area of the flash memory during a command write sequence. Writing a 0 to the FPVIOL flag has no
effect on FPVIOL. Writing a 1 to this bit clears it. While FPVIOL is set, it is not possible to launch a command or
start a command write sequence.
0 No protection violation detected.
1 Protection violation has occurred.
Access Error Flag. The FACCERR flag indicates an illegal access has occurred to the flash memory caused by
either a violation of the command write sequence, issuing an illegal flash command (see
Command Register
(FCCF = 0). Writing a 0 to the FACCERR flag has no effect on FACCERR. Writing a 1 to this bit clears it. While
FACCERR is set, it is not possible to launch a command or start a command write sequence.
0 No access error detected.
1 Access error has occurred.
Reserved, must be cleared.
Flag Indicating the Erase Verify Operation Status. When the FCCF flag is set after completion of an erase
verify command, the FBLANK flag indicates the result of the erase verify operation. The FBLANK flag is cleared
by the flash module when FCBEF is cleared as part of a new valid command write sequence. Writing to the
FBLANK flag has no effect on FBLANK.
0 Flash block verified as not erased.
1 Flash block verified as erased.
Reserved, should be cleared.
Flash Command Register (FxCMD)
0
0
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
0
6
(FxCMD)”), or the execution of a CPU STOP instruction while a command is executing
Figure 3-8. Flash Command Register (FxCMD)
Table 3-12. FxSTAT Field Descriptions
0
5
0
4
Description
FCMD
3
0
0
2
Section 3.4.3.6, “Flash
0
1
0
Memory
0
3-35