MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 595

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

changes to clock generator settings, it knows when a different BDC communication speed should be used.
The host programmer also knows that no unexpected change in bus frequency could occur to disrupt BDC
communications.
Normally, setting CLKSW should not be used for general debugging because there is no way to ensure the
application program does not change the clock generator settings. This is especially true in the case of
application programs that are not yet fully debugged.
After any reset (or at any other time), the host system can issue a SYNC command to determine the speed
of the BDC clock. CLKSW may be written using the serial WRITE_XCSR_BYTE command through the
BDC interface. CLKSW is located in the special XCSR byte register in the BDC module and it is not
accessible in the normal memory map of the ColdFire core. This means that no program running on the
processor can modify this register (intentionally or unintentionally).
The BKGD pin can receive a high- or low-level or transmit a high- or low-level. The following diagrams
show timing for each of these cases. Interface timing is synchronous to clocks in the target BDC, but
asynchronous to the external host. The internal BDC clock signal is shown for reference in counting
cycles.
Figure 26-16
host is asynchronous to the target so there is a 0–1 cycle delay from the host-generated falling edge to
where the target perceives the beginning of the bit time. Ten target BDC clock cycles later, the target senses
the bit level on the BKGD pin. Typically, the host actively drives the pseudo-open-drain BKGD pin during
host-to-target transmissions to speed up rising edges. Because the target does not drive the BKGD pin
during the host-to-target transmission period, there is no need to treat the line as an open-drain signal
during this period.
Figure 26-17
to the target MCU, there is a 0–1 cycle delay from the host-generated falling edge on BKGD to the
perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the
target to recognize it (at least two target BDC cycles). The host must release the low drive before the target
Freescale Semiconductor
SYNCHRONIZATION
PERCEIVED START
(TARGET MCU)
UNCERTAINTY
TRANSMIT 1
TRANSMIT 0
OF BIT TIME
BDC CLOCK
HOST
HOST
shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target MCU. The
shows the host receiving a logic 1 from the target MCU. Because the host is asynchronous
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 26-16. BDC Host-to-Target Serial Bit Timing
TARGET SENSES BIT LEVEL
10 CYCLES
Version 1 ColdFire Debug (CF1_DEBUG)
EARLIEST START
OF NEXT BIT
26-31