MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 196

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
BDM Command
ColdFire Core
8.2.1
D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they
can also be used as index registers.
8.2.2
These registers can be used as software stack pointers, index registers, or base address registers. They can
also be used for word and longword operations.
8-4
The values listed in this column represent the 8-bit BDM command code used when accessing the core registers via the 1-pin
BDM port. For more information see
similar to other ColdFire processors.)
If the given register is written using the MOVEC instruction, the 12-bit control register address (Rc) is also specified.
Store: 0xCE
Load: 0xEE
(D0, D1)
(D2-D7)
Reset
Reset
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
BDM: Load: 0x60 + n; n = 0-7 (Dn)
BDM: Load: 0x68 + n; n = 0–6 (An)
W
W
R
R
Data Registers (D0–D7)
Address Registers (A0–A6)
1
Store: 0x40 + n; n = 0-7 (Dn)
Store: 0x48 + n; n = 0–6 (An)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Registers D0 and D1 contain hardware configuration details after reset. See
Section 8.3.3.14, “Reset Exception”
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Status Register (SR)
Table 8-1. ColdFire Core Programming Model (continued)
Register
Chapter 26, “Version 1 ColdFire Debug (CF1_DEBUG).”
Figure 8-3. Address Registers (A0–A6)
Figure 8-2. Data Registers (D0–D7)
See
Section 8.3.3.14, “Reset Exception”
NOTE
for more details.
Width
(bits)
Address
16
Data
Access
R/W
Reset Value
0x27--
8
8
(These BDM commands are not
7
7
Access: User read/write
Access: User read/write
6
6
Written with
Freescale Semiconductor
MOVEC
5
5
No
BDM read/write
BDM read/write
4
4
3
3
2
2
2
Section/Page
1
1
8.2.8/8-8
0
0