MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 585

IC MCU 32BIT 256KB FLASH 100LQFP

MCF51EM256CLL

Manufacturer Part Number
MCF51EM256CLL
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51EMr
Datasheets

Specifications of MCF51EM256CLL

Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SCI, SPI
Peripherals
LCD, LVD, PWM, WDT
Number Of I /o
63
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
MCF51EM
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
RS-232, LIN
Maximum Clock Frequency
50 MHz
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
DEMOEM
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF51EM256CLL
Manufacturer:
FREESCALE
Quantity:
110
Part Number:
MCF51EM256CLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
L2EPC
L1EBL
20–18
L2PCI
Field
L2EA
L2DI
L2T
L1T
21
17
16
15
14
13
Level 2 data breakpoint invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a
trigger based on the occurrence of a data value other than the DBR contents.
0 No inversion
1 Invert data breakpoint comparators.
Enable level 2 address breakpoint. Setting an L2EA bit enables the corresponding address breakpoint. Clearing all
three bits disables the breakpoint.
Enable level 2 PC breakpoint.
0 Disable PC breakpoint
1 Enable PC breakpoint
Level 2 PC breakpoint invert.
0 The PC breakpoint is defined within the region defined by PBRn and PBMR.
1 The PC breakpoint is defined outside the region defined by PBRn and PBMR.
Level 2 trigger. Determines the logic operation for the trigger between the PC_condition and the (Address_range and
Data) condition where the inclusion of a Data_condition is optional. The ColdFire debug architecture supports the
creation of single or double-level triggers.
0 Level 2 trigger = PC_condition && (Address_range && Data_condition)
1 Level 2 trigger = PC_condition || (Address_range && Data_condition)
Level 1 trigger. Determines the logic operation for the trigger between the PC_condition and the (Address_range and
Data) condition where the inclusion of a Data_condition is optional. The ColdFire debug architecture supports the
creation of single or double-level triggers.
0 Level 1 trigger = PC_condition && (Address_range && Data_condition)
1 Level 1 trigger = PC_condition || (Address_range && Data_condition)
Enable level 1 breakpoint. Global enable for the breakpoint trigger.
0 Disables all level 1 breakpoints
1 Enables all level 1 breakpoint triggers
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
TDR Bit
Table 26-14. TDR Field Descriptions (continued)
20
19
18
Address breakpoint inverted. Breakpoint is based outside the
range between ABLR and ABHR.
Address breakpoint range. The breakpoint is based on the
inclusive range defined by ABLR and ABHR.
Address breakpoint low. The breakpoint is based on the
address in the ABLR.
Description
Description
Version 1 ColdFire Debug (CF1_DEBUG)
26-21

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