MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 523

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.3.2
Read: anytimeWrite: anytime
Freescale Semiconductor
DUTY[2:0]
LCLK[2:0]
SOURCE
Reset
LCDEN
Field
5:3
2:0
7
6
W
R
LCDIEN
LCD Control Register 1 (LCDC1)
LCD Driver Enable — LCDEN starts LCD-module-waveform generator.
0 All frontplane and backplane pins are disabled. The LCD module system is also disabled, and all LCD
1 LCD module driver system is enabled and frontplane and backplane waveforms are generated. All LCD pins
LCD Clock Source Select — The LCD module has two possible clock sources. This bit is used to select which
clock source is the basis for LCDCLK.
0 Selects the (external clock reference) as the LCD clock source.
1 Selects the alternate clock as the LCD clock source.
LCD Clock Prescaler — Used as a clock divider to generate the LCD module frame frequency as shown in
Equation
LCD module frame frequency calculations are provided in
LCD Module Frame Frequency
LCD Duty Select — DUTY[2:0] bits select the duty cycle of the LCD module driver.
000 Use 1 BP (1/1 duty cycle).
001 Use 2 BP (1/2 duty cycle).
010 Use 3 BP (1/3 duty cycle).
011 Use 4 BP (1/4 duty cycle). (Default)
100 Use 5 BP (1/5 duty cycle).
101 Use 6 BP (1/6 duty cycle).
110 Use 7 BP (1/7 duty cycle).
111 Use 8 BP (1/8 duty cycle).
0
7
waveform generation clocks are stopped. V
enabled using the LCD pin enable register (LCDPEN[x]) will output an LCD module driver waveform.The
backplane pins will output an LCD module driver backplane waveform based on the settings of DUTY[2:0].
Chargepump or resistor bias is enabled.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
24-1. LCD-module-duty-cycle configuration is used to determine the LCD module frame frequency.
0
0
= Unimplemented or Reserved
6
Figure 24-3. LCD Control Register 1 (LCDC1)
Table 24-5. LCDC0 Field Descriptions
((DUTY+1) x 8 x (4 + LCLK[2:0]) x Y)
0
0
5
=
LCDCLK
0
0
4
LL3
Description
is connected to V
Table
3
0
0
24-15./-21.
DD
where Y = 2,2,3,3,4,5,8,16 chosen
by module duty cycle configuration
where 30< LCDCLK < 39.063 kHz
internally
FCDEN
0
2
LCDWAI
0
1
LCD Driver Module
Eqn. 24-1
LCDSTP
0
0
24-7