MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 588

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
26.3.9
The ABLR and ABHR define regions in the processor’s data address space that can be used as part of the
trigger. These register values are compared with the address for each transfer on the processor’s high-speed
local bus. The trigger definition register (TDR) identifies the trigger as one of three cases:
The address breakpoint registers are accessible in supervisor mode using the WDEBUG instruction and
through the BDM port using the WRITE_DREG command using values shown in
Command Set Descriptions.”
26-24
Field
Mask
31–0
•
•
•
Identical to the value in ABLR
Inside the range bound by ABLR and ABHR inclusive
Outside that same range
ABHR
Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
Reset
ABLR
Reset
DRc: 0x09 (PBMR)
DRc: 0x0C (ABHR)
PC breakpoint mask. If using PBR0, this register must be initialized since it is undefined after reset.
0 The corresponding PBR0 bit is compared to the appropriate PC bit.
1 The corresponding PBR0 bit is ignored.
W
W
R
R
Address Breakpoint Registers (ABLR, ABHR)
0x0D (ABLR)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Version 1 ColdFire core devices implement a 24-bit, 16 MB address map.
When programming these registers with a 32-bit address, the upper byte
must be zero-filled.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 26-12. Program Counter Breakpoint Mask Register (PBMR)
Figure 26-13. Address Breakpoint Registers (ABLR, ABHR)
Table 26-17. PBMR Field Descriptions
NOTE
Description
Address
Mask
Access: Supervisor write-only
Access: Supervisor write-only
8
8
7
7
Section 26.4.1.4, “BDM
6
6
Freescale Semiconductor
5
5
BDM write-only
BDM write-only
4
4
3
3
2
2
1
1
0
0