MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 507

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.2.2.2
This register specifies the period of the counter in terms of PDB source clock cycles. When the counter
reaches this value, it will be reset back to all zeros. If PDBSC_CONT is set to one, the count will begin
anew.
22.2.2.3
This register can be used to read the current value of the counter. It is READ ONLY.
This register is set to zero when PDBSC_EN = 0. The count does not start until a hardware or software
trigger event occurs.
22.2.2.4
This register can be used to read and write the value used to schedule the PDB IDelay interrupt. This
feature can be used to schedule an independent interrupt at some point in the PDB cycle.
PDBSC_IE must be set in order for an interrupt to be issued as a result of the count value equaling
IDELAY. However, PDBSC_IF will be set whenever COUNT=IDELAY.
Freescale Semiconductor
RESET:
RESET:
RESET:
W
W
W
R
R
R
15
15
15
1
0
1
PDB Modulus Register (PDBMOD)
PDB Counter Register (PDBCNT)
PDB Interrupt Delay Register (PDBIDLY)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
14
14
14
1
0
1
= Reserved or unused
= Reserved or unused
= Reserved or unused
13
13
13
1
0
1
Figure 22-6. PDB Interrupt Delay Register (PDBIDLY)
12
12
12
1
0
1
Figure 22-4. PDB Modulus Register (PDBMOD)
Figure 22-5. PDB Counter Register (PDBCNT)
11
11
11
1
0
1
10
10
10
1
1
0
9
1
9
0
9
1
8
1
8
0
8
1
COUNT
IDELAY
MOD
7
1
7
0
7
1
6
1
6
0
6
1
5
1
5
0
5
1
4
1
4
0
4
1
Programmable Delay Block (PDB)
3
1
3
0
3
1
2
1
2
0
2
1
1
1
1
0
1
1
22-7
0
1
0
0
0
1