MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 265

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.3.4
Freescale Semiconductor
IREFST
1
DMX32
DRST
Field
TRIM
Field
DRS
7-6
7:0
FTRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM mode, FTRIM
gets loaded with a value of 1’b0.
5
4
Reset:
W
R
ICS Status and Control (ICSSC)
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (in other words, bit 1 adjusts twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
DCO Range Status — The DRST read field indicates the current frequency range for the FLL output, DCOOUT.
See
synchronization between clock domains. Writing the DRS bits to 2’b11 is ignored and the DRST bits remain with
the current setting.
DCO Range Select — The DRS field selects the frequency range for the FLL output, DCOOUT. Writes to the
DRS field while the LP bit is set are ignored.
00
01
10
11
DCO Maximum frequency with 32.768 kHz reference — The DMX32 bit controls whether or not the DCO
frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. See
0 DCO has default range of 25%.
1 DCO is fined tuned for maximum frequency with 32.768 kHz reference.
Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST
bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock
domains.
0 Source of reference clock is external clock.
1 Source of reference clock is internal clock.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table
Low range.
Mid range.
High range.
Reserved.
7
0
Table 11-11. ICS Status and Control Register Field Descriptions
11-12. The DRST field does not update immediately after a write to the DRS field due to internal
DRST
DRS
Figure 11-10. ICS Status and Control Register (ICSSC)
Table 11-10. ICS Trim Register Field Descriptions
0
6
DMX32
0
5
IREFST
1
4
Description
Description
0
3
CLKST
0
2
OSCINIT
Internal Clock Source (ICS)
0
1
Table
11-12.
FTRIM
0
1
11-11