MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 104

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Memory
If the FPVIOL flag is set in the FxSTAT register, the user must clear the FPVIOL flag before starting
another command write sequence (see
3.4.7
3.4.7.1
If a command is active (FCCF = 0) when the MCU enters wait mode, the active command and any buffered
command will be completed.
3.4.7.2
If a command is active (FCCF = 0) when the MCU enters stop mode, the operation will be aborted and, if
the operation is program or erase, the flash array data being programmed or erased may be corrupted and
the FCCF and FACCERR flags will be set. If active, the high voltage circuitry to the flash array will
immediately be switched off when entering stop mode. Upon exit from stop mode, the FCBEF flag is set
and any buffered command will not be launched. The FACCERR flag must be cleared before starting a
command write sequence (see
3.4.7.3
In background debug mode, the FxPROT register is writable without restrictions. If the MCU is unsecured,
then all flash commands listed in
and erase verify commands can be executed.
3.5
The MCF51EM256 series microcontrollers include circuitry to prevent unauthorized access to the contents
of flash and RAM memory. When security is engaged, BDM access is restricted to the upper byte of the
ColdFire CSR, XCSR, and CSR2 registers. RAM, flash memory, peripheral registers and most of the CPU
register set are not available via BDM. Programs executing from internal memory have normal access to
all microcontroller memory locations and resources.
The MCF51EM256 series devices include two independent flash blocks in support of the robust update
feature for on-chip flash. Each flash block has its own set of two security bits as described below. Security
must be clear ON BOTH flash blocks in order for the device to be unsecured. This allows the device to
3-48
4. Writing an invalid command if the address written in the command write sequence was in a
protected area of the flash array.
Security
Operating Modes
WAIT Mode
Stop Mode
Background Debug Mode
As active commands are immediately aborted when the MCU enters stop
mode, it is strongly recommended that the user does not use the STOP
instruction during program or erase operations.
Active commands will continue when the MCU enters wait mode. Use of
the STOP instruction when SOPT1[WAITE]=1 is acceptable.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Section 3.4.4.2, “Command Write
Table 3-14
Section 3.4.3.5, “Flash Status Register
can be executed. If the MCU is secured, only the mass erase
NOTE
Sequence”).
(FxSTAT)”).
Freescale Semiconductor