MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 379

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The coherency sequence can be manually reset by writing to the channel status/control register
(TPMCnSC).
An output compare event sets a flag bit (CHnF) which may optionally generate a CPU-interrupt request.
16.4.2.3
This type of PWM output uses the normal up-counting mode of the timer counter (CPWMS=0) and can
be used when other channels in the same TPM are configured for input capture or output compare
functions. The period of this PWM signal is determined by the value of the modulus register
(TPMMODH:TPMMODL) plus 1. The duty cycle is determined by the setting in the timer channel register
(TPMCnVH:TPMCnVL). The polarity of this PWM signal is determined by the setting in the ELSnA
control bit. 0% and 100% duty cycle cases are possible.
The output compare value in the TPM channel registers determines the pulse width (duty cycle) of the
PWM signal
width. If ELSnA=0, the counter overflow forces the PWM signal high, and the output compare forces the
PWM signal low. If ELSnA=1, the counter overflow forces the PWM signal low, and the output compare
forces the PWM signal high.
When the channel value register is set to 0x0000, the duty cycle is 0%. 100% duty cycle can be achieved
by setting the timer-channel register (TPMCnVH:TPMCnVL) to a value greater than the modulus setting.
This implies that the modulus setting must be less than 0xFFFF in order to get 100% duty cycle.
Because the TPM may be used in an 8-bit MCU, the settings in the timer channel registers are buffered to
ensure coherent 16-bit updates and to avoid unexpected PWM pulse widths. Writes to any of the registers
TPMCnVH and TPMCnVL, actually write to buffer registers. In edge-aligned PWM mode, values are
transferred to the corresponding timer-channel registers according to the value of CLKS bits, so:
Freescale Semiconductor
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If (CLKS[1:0] = 00), the registers are updated when the second byte is written
If (CLKS[1:0] not = 00), the registers are updated at the next change of the TPM counter (end of
the prescaler counting) after the second byte is written.
If (CLKS[1:0] = 00), the registers are updated when the second byte is written
If (CLKS[1:0] not = 00), the registers are updated after the both bytes were written, and the TPM
counter changes from (TPMMODH:TPMMODL - 1) to (TPMMODH:TPMMODL). If the TPM
counter is a free-running counter then the update is made when the TPM counter changes from
0xFFFE to 0xFFFF.
(Figure
TPM
Edge-Aligned PWM Mode
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
CHn
OVERFLOW
16-14). The time between the modulus overflow and the output compare is the pulse
Figure 16-14. PWM Period and Pulse Width (ELSnA=0)
PULSE
WIDTH
PERIOD
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
OVERFLOW
COMPARE
OUTPUT
Timer/PWM Module(TPM)
16-17