MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 468

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Analog-to-Digital Converter (S08ADC16)
21.4.4
The Data Result Registers (ADCRHA:ADCRLA to ADCRHn:ADCRLn) contain the result of an ADC
conversion of the channel selected by the respective status and channel control register
(ADCSC1A:ADCSC1n). For every ADCSC1A:ADCSC1n status and channel control register, there is a
respective ADCRHA:ADCRLA to ADCRHn:ADCRLn data result register. Consult the module
introduction for information on the number of ADCRHn:ADCRLn registers specific to this MCU.Reading
ADCRHn prevents the ADC from transferring subsequent conversion results into the result registers until
ADCRLn is read. If ADCRLn is not read until after the next conversion is completed, the intermediate
conversion result is lost. In 8-bit single-ended mode, there is no interlocking with ADCRLn.
ADCRHn contains the upper bits of the result of a conversion based on the conversion mode. ADCRLn
contains the lower eight bits of the result of a conversion, or all eight bits of an 8-bit single-ended
conversion. Unused bits in the ADCRHn register are cleared in unsigned right justified modes and carry
the sign bit (MSB) in sign extended 2’s complement modes. For example when configured for 10-bit
single-ended mode, D[15:10] are cleared. When configured for 11-bit differential mode, D[15:10] carry
the sign bit (bit 10 extended through bit 15).
Table 21-10
21-12
16b single-ended
12b single-ended
16b differential
13b differential
11b differential
Conversion
Mode
Reset:
Reset:
W
W
R
R
Data Result Registers (ADCRHA:ADCRLA to ADCRHn:ADCRLn)
describes the behavior of the data result registers in the different modes of operation.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
7
0
7
0
S
D
S
0
S
D
D
S
0
S
D
D
S
S
0
Figure 21-5. Data Result High Register (ADCRHn)
Figure 21-6. Data Result Low Register (ADCRLn)
0
0
6
6
Table 21-10. Data Result Register Description
D
D
S
0
S
D
D
D
D
S
Data Result Register bits
D
D
D
D
S
0
0
5
5
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
0
4
4
D
D
D
D
D
D[15:8]
D[7:0]
D
D
D
D
D
D
D
D
D
D
0
0
3
3
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
0
0
2
2
D
D
D
D
D
signed 2’s complement
unsigned right justified
unsigned right justified
Freescale Semiconductor
0
0
1
1
sign extended 2’s
sign extended 2’s
complement
complement
Format
0
0
0
0