MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 629

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
1
sub.l
suba.l
subi.l
subq.l
subx.l
swap.w
tas.b
tpf
tpf.l
tpf.w
trap
tst.b
tst.l
tst.w
unlk
wddata.b
wddata.l
wddata.w
Instruction
During normal exception processing, the PSTB is loaded with two successive 0x1C entries indicating the exception
processing state. The exception stack write operands, as well as the vector read and target address of the exception
handler may also be displayed.
Exception Processing:
A similar set of PST/DD values is generated in response to an emulator mode excetion. For these events (caused
by a debug interrupt or properly-enabled trace exception), the initial PST values are 0x1D, 0x1D and the remaining
sequence is equivalent to normal exception processing.
The PST
Exception Processing:
The initial references at address 0 and 4 are never captured nor displayed because these accesses are treated as
instruction fetches.
For all types of exception processing, the PST = 0x1C (or 0x1D) value is driven for two trace buffer entries.
{PST = 0x0B,DD = destination},
{PST = 0x0B,DD = destination},
{PST = 0x0B,DD = source},
PST = 0x1C, 0x1C,
PST = 0x05,{PST = 0x0[DE],DD = target}
PST = 0x1C, 0x1C,
PST = 0x05,{PST = 0x0[DE],DD = target}
/
Table 26-27. PST/DDATA Specification for User-Mode Instructions (continued)
DDATA specification for the reset exception is shown below:
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Dy,<ea>x
<ea>y,Ax
#<data>,Dx
#<data>,<ea>x
Dy,Dx
Dx
<ea>x
#<data>
#<data>
<ea>x
<ea>y
<ea>y
Ax
#<data>
<ea>y
<ea>y
<ea>y
Operand Syntax
PST = 0x01, {PST = 0x0B, DD = source}, {PST = 0x0B, DD = destination}
PST = 0x01, {PST = 0x0B, DD = source operand}
PST = 0x01
PST = 0x01, {PST = 0x0B, DD = source}, {PST = 0x0B, DD = destination}
PST = 0x01
PST = 0x01
PST = 0x01, {0x08, source}, {0x08, destination}
PST = 0x01
PST = 0x01
PST = 0x01
PST = 0x01
PST = 0x01, {PST = 0x08, DD = source operand}
PST = 0x01, {PST = 0x0B, DD = source operand}
PST = 0x01, {PST = 0x09, DD = source operand}
PST = 0x01, {PST = 0x0B, DD = destination operand}
PST = 0x04, {PST = 0x08, DD = source operand}
PST = 0x04, {PST = 0x0B, DD = source operand}
PST = 0x04, {PST = 0x09, DD = source operand}
1
// initial PC
// handler PC
PST/DDATA
// stack frame
// stack frame
// vector read
Version 1 ColdFire Debug (CF1_DEBUG)
26-65