MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 58

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Memory
Regions within the memory map are subject to restrictions with regard to the types of CPU accesses
allowed. These are outlined in
(and would typically generate a system reset in response to the error termination).
Consistent with past ColdFire devices, flash configuration data is located at 0x(00)00_0400. The slave
peripherals section of the memory map is further broken down as shown in
3-2
Port Control Module Port I/O Control Module
Port Control Module Port I/O Control Module
Port Control Module Port I/O Control Module
Port Control Module Port I/O Control Module
Port Control Module Port I/O Control Module
Port Control Module Port I/O Control Module
Port I/O Module
Port I/O Module
Port I/O Module
Port I/O Module
Port I/O Module
Port I/O Module
Peripheral
RGPIO
1
2
3
Allowed access types are peripheral specific. The peripheral bus bridge will serialize 16 and 32-bit
accesses into multiple 8-bit accesses. When using 8-bit peripherals, care must be taken to ensure that all
accesses are properly aligned and only desired 8-bit locations are accessed.
Allowed access types are peripheral specific. The peripheral bus bridge will serialize 32-bit accesses into
multiple 16-bit accesses. When using 16-bit peripherals, care must be taken to ensure that all accesses
are properly aligned and only desired 16-bit locations are accessed.
LCD registers require several cycles between write accesses. Only byte writes should be used to write to
these registers. Finally, consecutive writes must be separated by at least one non-write cycle.
0x(FF)FF_E000
0x(FF)FF_8000
0x(FF)FF_8700
0x(00)C0_0000
Base Address
0x(00)00_0000
0x(00)80_0000
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Rapid General Purpose I/O
General Purpose I/O With Set/Clear/Toggle Functionality
General Purpose I/O With Set/Clear/Toggle Functionality
General Purpose I/O With Set/Clear/Toggle Functionality
General Purpose I/O With Set/Clear/Toggle Functionality
General Purpose I/O With Set/Clear/Toggle Functionality
General Purpose I/O With Set/Clear/Toggle Functionality
Table 3-1. CPU Access Type Allowed by Region
Table
Table 3-2. High Level Peripheral Memory Map
Flash
RAM
Rapid GPIO
8-bit Peripherals
16-bit Peripherals
LCD registers
3-1. Non-supported access types terminate the bus cycle with an error
Region
Description
3
1
2
Byte
—
x
x
x
x
x
Word
Read
x
x
x
x
x
x
Long
x
x
x
x
x
x
Instance Name
RGPIO
Table
Byte
PTC
PTC
PTD
PTD
PTA
PTB
PTB
PTE
PTE
PTF
PTF
PTA
—
—
x
x
x
x
3-2.
Word
Write
Freescale Semiconductor
—
—
x
x
x
x
0x(FF)FF_80C0
0x(FF)FF_80C8
0x(00)C0_0000
0x(FF)FF_8000
0x(FF)FF_8008
0x(FF)FF_8040
0x(FF)FF_8048
0x(FF)FF_8080
0x(FF)FF_8088
0x(FF)FF_8100
0x(FF)FF_8108
0x(FF)FF_8140
0x(FF)FF_8148
Base Address
Long
—
x
x
x
x
x