MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 266

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Internal Clock Source (ICS)
11-12
r
OSCINIT
CLKST
FTRIM
Field
3-2
1
0
Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits don’t update
immediately after a write to the CLKS bits due to internal synchronization between clock domains.
00
01
10
11
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared.
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 1.11
Table 11-11. ICS Status and Control Register Field Descriptions (continued)
Output of FLL is selected.
FLL Bypassed, Internal reference clock is selected.
FLL Bypassed, External reference clock is selected.
1
Reserved.
DRS DMX32
The resulting bus clock frequency should not exceed the maximum specified bus
clock frequency of the device.
00
01
10
11
0
1
0
1
0
1
31.25 - 39.0625 kHz
31.25 - 39.0625 kHz
31.25 - 39.0625 kHz
Table 11-12. DCO frequency range
Reference range
32.768 kHz
32.768 kHz
32.768 kHz
Reserved
Description
FLL factor
1024
1216
1536
1824
512
608
1
DCO range
16 - 20 MHz
32 - 40 MHz
48 - 60 MHz
19.92 MHz
39.85 MHz
59.77 MHz
Freescale Semiconductor