MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 248

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Interrupt Controller (CF1_INTC)
10.3.5
The INTC_CFRC register provides a simple memory-mapped mechanism to clear a given bit in the
INTC_FRC register to negate a specific level interrupt request. The data value on the register write causes
the appropriate bit in the INTC_FRC register to be cleared. Attempted reads of this register generate an
error termination.
This register is provided so interrupt service routines can negate a forced interrupt request without the need
to perform a read-modify-write sequence on the INTC_FRC register.
10-12
Offset: CF1_INTC_BASE + 0x1F (INTC_CFRC)
Field
Field
SET
Reset
CLR
7–6
5–0
7–6
5–0
W
R
Reserved, must be cleared.
For data values within the 56–62 range, the corresponding bit in the INTC_FRC register is set, as defined below.
0x38 Bit 56, INTC_FRC[LVL7] is set
0x39 Bit 57, INTC_FRC[LVL6] is set
0x3A Bit 58, INTC_FRC[LVL5] is set
0x3B Bit 59, INTC_FRC[LVL4] is set
0x3C Bit 60, INTC_FRC[LVL3] is set
0x3D Bit 61, INTC_FRC[LVL2] is set
0x3E Bit 62, INTC_FRC[LVL1] is set
Note: Data values outside this range do not affect the INTC_FRC register. It is recommended the data values be
Reserved, must be cleared.
For data values within the 56–62 range, the corresponding bit in the INTC_FRC register is cleared, as defined below.
0x38 Bit 56, INTC_FRC[LVL7] is cleared
0x39 Bit 57, INTC_FRC[LVL6] is cleared
0x3A Bit 58, INTC_FRC[LVL5] is cleared
0x3B Bit 59, INTC_FRC[LVL4] is cleared
0x3C Bit 60, INTC_FRC[LVL3] is cleared
0x3D Bit 61, INTC_FRC[LVL2] is cleared
0x3E Bit 62, INTC_FRC[LVL1] is cleared
Note: Data values outside this range do not affect the INTC_FRC register. It is recommended the data values be
INTC Clear Interrupt Force Register (INTC_CFRC)
0
0
7
restricted to the 0x38–0x3E (56–62) range to ensure compatibility with future devices.
restricted to the 0x38–0x3E (56–62) range to ensure compatibility with future devices.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
0
0
6
Table 10-8. INTC_CFRC Field Descriptions
Table 10-7. INTC_SFRC Field Descriptions
Figure 10-6. INTC_CFRC Register
0
5
0
4
Description
Description
3
0
CLR
0
2
Freescale Semiconductor
0
1
Access: Write-only
0
0