MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 148

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Rapid GPIO (RGPIO)
5.3.3
The RGPIO_ENB register configures the corresponding package pin as a RGPIO pin instead of the normal
GPIO pin mapped onto the peripheral bus.
The RGPIO_ENB register is read/write. At reset, all bits in the RGPIO_ENB are cleared, disabling the
RGPIO functionality.
5.3.4
The RGPIO_CLR register provides a mechanism to clear specific bits in the RGPIO_DATA by performing
a simple write. Clearing a bit in RGPIO_CLR clears the corresponding bit in the RGPIO_DATA register.
Setting it has no effect. The RGPIO_CLR register is write-only; reads of this address return the
RGPIO_DATA register.
5-8
Field
DATA
Offset: RGPIO_Base + 0x4 (RGPIO_ENB)
Field
Offset: RGPIO_Base + 0x6 (RGPIO_CLR)
15–0
15–0
ENB
Reset
Reset
W
W
R
R
RGPIO data.
0 A properly-enabled RGPIO output pin is driven with a logic 0, or a properly-enabled RGPIO input pin was read as
1 A properly-enabled RGPIO output pin is driven with a logic 1, or a properly-enabled RGPIO input pin was read as
RGPIO enable.
0 The corresponding package pin is configured for use as a normal GPIO pin, not a RGPIO
1 The corresponding package pin is configured for use as a RGPIO pin
—
15
15
0
a logic 0
a logic 1
RGPIO Pin Enable (RGPIO_ENB)
RGPIO Clear Data (RGPIO_CLR)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
—
14
14
0
—
13
13
0
Figure 5-6. RGPIO Clear Data Register (RGPIO_CLR)
Figure 5-5. RGPIO Enable Register (RGPIO_ENB)
—
12
12
0
Table 5-6. RGPIO_DATA Field Descriptions
Table 5-7. RGPIO_ENB Field Descriptions
11
11
—
0
—
10
10
0
—
0
9
9
Description
Description
—
8
0
8
ENB
CLR
—
0
7
7
—
0
6
6
—
0
5
5
—
0
4
4
—
3
0
3
Freescale Semiconductor
Access: Read/write
—
Access: Write-only
0
2
2
—
0
1
1
—
0
0
0