MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 29

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.3.3
Table 1-6
Freescale Semiconductor
OSCOUT1
OSCOUT2
ICSOUT
ICSLCLK
ICSERCLK
ICSIRCLK
ICSFFCLK
LPOCLK
TMRCLK1 &
TMRCLK2
MTIM1 Output
(MTCK)
TPMCLK
ADACK
CLKOUT
Clock
describes each of the system clocks.
System Clocks
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
This is the direct output of XOSC1 and is used as the clock source for the independent real time
clock (IRTC) module and LCD. This signal can also be consumed by the ICS. See
“Internal Clock Source (ICS)
This is the direct output of XOSC2, and is normally consumed by the ICS. It can also be consumed
by the LCD module.
This clock source is used as the CPU clock and is divided by 2 to generate the peripheral bus clock.
Control bits in the ICS control registers determine which of three clock sources is connected:
This clock drives the CPU, debug, RAM, and BDM directly and is divided by 2 to clock all peripherals
(BUSCLK).
See
This clock source runs at 1/2 the rate of the low frequency DCO (10/20 MHz digitally controlled
oscillator). Development tools can select this internal self-clocked source to speed up BDC
communications in systems where the bus clock is slow. Please see
their accompanying text for details.
ICS external reference clock — This is the external reference clock and can be selected as an
alternate clock for the ADCs.
ICS internal reference clock — This is the internal reference clock and it is not used outside of the
ICS module.
ICS fixed-frequency clock — This generates the fixed frequency clock (FFCLK) after being
synchronized to the bus clock. The FFCLK can be selected as clock source for the MTIM and TPM
modules. The frequency of the FFCLK is determined by the settings of the ICS.
Low-power oscillator clock — This clock is generated from an internal low-power oscillator that is
completely independent of the ICS module. The LPOCLK can be selected as the clock source to the
COP.
Optional external clock sources for the MTIMs. These clocks must be limited to one-quarter the
frequency of the bus clock for synchronization. The SIMIPS register (see
Options Register
The MTIM1 output can be used in place of TMRCLK1, TMRCLK2 and TPMCLK as the external clock
source into the MTIM2, MTIM3 and TPM (see
(SIMCO)”). This allows the user to use MTIM1 as a non-power-of-two prescaler of the bus clock.
Optional external clock source for the TPM module (see
Register
synchronization.
Each ADC module also has an internally generated asynchronous clock which allows it to run in
STOP mode (ADACK). This signal is not available externally.
This is an optional output of the device which can be used to deliver any of a number of the on-chip
clocks, including the crystal oscillator outputs, bus clock, etc. See
Options Register
• Internal reference clock
• External reference clock
• Frequency-locked loop (FLL) output
Chapter 11, “Internal Clock Source
(SIMCO)”). This clock must be limited to one-quarter the frequency of the bus clock for
(SIMCO)”) determines which clock source supplies the TCLK input to the MTIMs.
(SIMCO),” for details.
Table 1-6. System Clocks
and
Chapter 17, “Independent Real Time Clock
(ICS),” for details on configuring the ICSOUT clock.
Description
Section 7.7.14, “SIM Clock Options Register
Section 7.7.14, “SIM Clock Options
Section 7.7.14, “SIM Clock
Figure
Section 7.7.14, “SIM Clock
11-6,
(IRTC),” for details.
Figure
Chapter 11,
Device Overview
26-2, and
1-11