MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 314

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16-Bit Serial Peripheral Interface (SPI16)
the flag bits to determine what event caused the interrupt. The service routine should also clear the flag
bit(s) before returning from the ISR (usually near the beginning of the ISR).
13.4.11.1 MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the
MODF feature (see
changed:
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the
interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing
process which is described in
13.4.11.2 SPRF
SPRF occurs when new data has been received and copied to the SPI receive data buffer. In 8-bit mode,
SPRF is set only after all 8 bits have been shifted out of the shift register and into SPIxDL. In 16-bit mode,
SPRF is set only after all 16 bits have been shifted out of the shift register and into SPIxDH:SPIxDL.
Once SPRF is set, it does not clear until it is serviced. SPRF has an automatic clearing process which is
described in
before the end of the next transfer (i.e. SPRF remains active throughout another transfer), the latter
transfers will be ignored and no new data will be copied into the SPIxDH:SPIxDL.
13.4.11.3 SPTEF
SPTEF occurs when the SPI transmit buffer is ready to accept new data. In 8-bit mode, SPTEF is set only
after all 8 bits have been moved from SPIxDL into the shifter. In 16-bit mode, SPTEF is set only after all
16 bits have been moved from SPIxDH:SPIxDL into the shifter.
Once SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process which is
described in
13.4.11.4 SPMF
SPMF occurs when the data in the receive data buffer is equal to the data in the SPI match register. In 8-bit
mode, SPMF is set only after bits 8–0 in the receive data buffer are determined to be equivalent to the value
in SPIxML. In 16-bit mode, SPMF is set after bits 15–0 in the receive data buffer are determined to be
equivalent to the value in SPIxMH:SPIxML.
13.4.11.5 TNEAREF
TNEAREF flag is set when only one 16-bit word or 2 8-bit bytes of data remain in the transmit FIFO
provided SPIxC3[5] = 0 or when only two 16bit word or 4 8-bit bytes of data remain in the transmit FIFO
provided SPIxC3[5] =1. If FIFOMODE is not enabled this bit should be ignored.
13-28
•
MSTR=0, The master bit in SPIxC1 resets.
Section 13.3.4, “SPI Status Register
Section 13.3.4, “SPI Status Register
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table
13-2). Once MODF is set, the current transfer is aborted and the following bit is
Section 13.3.4, “SPI Status Register
(SPIxS).” In the event that the SPRF is not serviced
(SPIxS).”
(SPIxS).”
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