MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 28

IC MCU 32BIT 256KB FLASH 100LQFP

MCF51EM256CLL

Manufacturer Part Number
MCF51EM256CLL
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51EMr
Datasheets

Specifications of MCF51EM256CLL

Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SCI, SPI
Peripherals
LCD, LVD, PWM, WDT
Number Of I /o
63
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
MCF51EM
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
RS-232, LIN
Maximum Clock Frequency
50 MHz
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
DEMOEM
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF51EM256CLL
Manufacturer:
FREESCALE
Quantity:
110
Part Number:
MCF51EM256CLL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Device Overview
1-10
Clock Check
& Select
Note: The ADCs have minimum and maximum frequency requirements. See the ADC chapter and the MCF51EM256 Series Data
Sheet. Flash memory has frequency requirements for program and erase operations. Each ADC also has its own internal
asynchronous clock source, which is not shown above.
* The fixed frequency clock (FFCLK) is internally synchronized to the bus clock (BUSCLK) and must not exceed one half of the bus
clock frequency.
ICS
Oscillator Control
OSCOUT2
to LCD
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
ICSERCLK
ICSFFCLK
ICSOUT
XOSC2
RGPIO
DBG
CPU
ICSLCLK
OSCOUT1
1 kHz
LPO
÷2
÷2
XOSC1
RAM
LPOCLK
Figure 1-3. Clock Distribution Diagram
BUSCLK
SYNC*
Separate Power Domain
BDM
COP
Independent
OSCOUT1&2
RTC
TPMCLK
LCD
TPM
FFCLK*
Controller
Interrupt
MTIM2
MTIM3
TMRCLK1
MTCK
ADACK
ADC 1
ADC 2
ADC 3
ADC 4
MTIM1
TMRCLK2
PDB
VREG
FLASH
KBI &
GPIO
Freescale Semiconductor
IIC
SPI1
SPI2
SPI3
PRACMP1
PRACMP2
SCI1
SCI2
SCI3

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