MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 116

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.2.2.3
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTxDS[n]). When high drive is selected, a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, ensure that the total
current source and sink limits for the MCU are not exceeded. Drive strength selection is intended to affect
the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin to drive
a greater load with the same switching speed as a low drive enabled pin into a smaller load. Because of
this, the EMC emissions may be affected by enabling pins as high drive.
4-6
Reset:
Reset:
PTxSEn
PTxDSn
Field
Field
7–0
7–0
W
W
R
R
PTxDS7
PTxSE7
Output Slew Rate Enable for Port x Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTx pin. For Port x pins configured as inputs, these bits have no effect.
0 Output slew rate control disabled for Port x bit n.
1 Output slew rate control enabled for Port x bit n.
Output Drive Strength Selection for Port x Bits — Each of these control bits selects between low and high
output drive for the associated PTx pin. For Port x pins configured as inputs, these bits have no effect.
0 Low output drive strength selected for Port x bit n.
1 High output drive strength selected for Port x bit n.
0
Port x Drive Strength Selection Register (PTxDS)
0
7
7
PTE6, PTE5 and PTE4 do not support the slew rate control, and the register
bits PTESE6, PTESE5 and PTESE4 have no effect on these pins.
PTE6, PTE5 and PTE4 do not support the drive strength control, and the
register bits PTEDS6, PTEDS5 and PTEDS4 have no effect on these pins.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 4-4. Drive Strength Selection for Port x Register (PTxDS)
PTxDS6
PTxSE6
Figure 4-3. Slew Rate Enable for Port x Register (PTxSE)
0
0
6
6
Table 4-8. PTxSE Field Descriptions
Table 4-9. PTxDS Field Descriptions
PTxSE5
PTxDS5
0
0
5
5
PTxSE4
PTxDS4
NOTE
NOTE
0
0
4
4
Description
Description
PTxSE3
PTxDS3
3
0
3
0
PTxDS2
PTxSE2
0
2
0
2
PTxDS1
Freescale Semiconductor
PTxSE1
0
0
1
1
PTxDS0
PTxSE0
0
0
0
0