MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 210

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ColdFire Core
The selection of the format value provides some limited debug support for porting code from M68000
applications. On M68000 family processors, the SR was located at the top of the stack. On those
processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE
is attempted using this old format, it generates a format error on a ColdFire processor.
If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second
longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address
after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the
second longword operand within the stack frame.
8.3.3.10
The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing
system calls. The TRAP instruction may be used to change from user to supervisor mode.
This set of 16 instructions provides a similar but expanded functionality compared to the S08’s SWI
(software interrupt) instruction. Do not confuse these instructions and their functionality with the
software-scheduled interrupt requests, which are handled like normal I/O interrupt requests by the
interrupt controller. The processing of the software-scheduled IRQs can be masked, based on the interrupt
priority level defined by the SR[I] field.
8.3.3.11
If execution of a valid instruction is attempted but the required hardware is not present in the processor, an
unsupported instruction exception is generated. The instruction functionality can then be emulated in the
exception handler, if desired.
All ColdFire cores record the processor hardware configuration in the D0 register immediately after the
negation of RESET. See
For this device, attempted execution of valid integer divide opcodes and CAU instructions result in the
unsupported instruction exception.
8.3.3.12
Interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from
the interrupt controller using an IACK cycle or using the previously-supplied vector number, under control
of CPUCR[IAE]. See
controller.
8.3.3.13
The default operation of the V1 ColdFire processor is the generation of an illegal address reset event if a
fault-on-fault halt condition is detected. If CPUCR[ARD] is set, the reset is disabled and the processor is
halted as detailed below.
If a ColdFire processor encounters any type of fault during the exception processing of another fault, the
processor immediately halts execution with the catastrophic fault-on-fault condition. A reset is required to
to exit this state.
8-18
TRAP Instruction Exception
Unsupported Instruction Exception
Interrupt Exception
Fault-on-Fault Halt
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Chapter 10, “Interrupt Controller (CF1_INTC),”
Section 8.3.3.14, “Reset Exception,”
for details.
for details on the interrupt
Freescale Semiconductor