MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 593

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The processor’s run/stop/halt status is always accessible in XCSR[CPUHALT,CPUSTOP]. Additionally,
CSR[27–24] indicate the halt source, showing the highest priority source for multiple halt conditions. This
field is cleared by a read of the CSR. A processor halt due to the PSTB full condition as indicated by
CSR2[PSTH] is also reflected in CSR[BKPT]. The debug GO command clears CSR[26–24] and
CSR2[PSTBH].
26.4.1.2
BDC serial communications use a custom serial protocol first introduced on the M68HC12 Family of
microcontrollers and later used in the M68HCS08 family. This protocol assumes that the host knows the
Freescale Semiconductor
PSTB full condition
after reset negated
for ≥2 bus clocks
for POR or BDM
BACKGROUND
BKGD held low
Halt Source
command
reset
Background Debug Serial Interface Controller (BDC)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Halt Timing
Immediate
Pending
Pending
BDM enabled and
BDM disabled or
Flash unsecure
flash unsecure
Table 26-23. CPU Halt Sources (continued)
Flash secure
flash secure
PSTB
Illegal command response and BACKGROUND command is ignored.
PSTB obtrusive recording mode pends halt in the processor if the trace
buffer reaches its full threshold (full is defined as before the buffer is
overwritten). When a pending condition is asserted, the processor halts
at the next sample point.
Enters debug mode with XCSR[ENBDM, CLKSW] set. The full set of
BDM commands is available and debug can proceed.
If the core is reset into a debug halt condition, the processor’s response
to the GO command depends on the BDM command(s) performed while
it was halted. Specifically, if the PC register was loaded, the GO
command causes the processor to exit halted state and pass control to
the instruction address in the PC, bypassing normal reset exception
processing. If the PC was not loaded, the GO command causes the
processor to exit halted state and continue reset exception processing.
Enters debug mode with XCSR[ENBDM, CLKSW] set. The allowable
commands are limited to the always-available group. A GO command to
start the processor is not allowed. The only recovery actions in this mode
are:
• Issue a BDM reset setting CSR2[BDFR] with CSR2[BDHBR] cleared
• Erase the flash to unsecure the memory and then proceed with debug
• Power cycle the device with the BKGD pin held high to reset into the
Processor is
Processor is
and the BKGD pin held high to reset into normal operating mode
normal operating mode
stopped
running
Halt is made pending in the processor. The processor
samples for pending halt and interrupt conditions
once per instruction. When a pending condition is
asserted, the processor halts execution at the next
sample point.
Processing of the BACKGROUND command is
treated in a special manner. The processor exits the
stopped mode and enters the halted state, at which
point all BDM commands may be exercised. When
restarted, the processor continues by executing the
next sequential instruction (the instruction following
STOP).
Description
Version 1 ColdFire Debug (CF1_DEBUG)
26-29