MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 228

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Multiply-Accumulate Unit (MAC)
9.3
The MAC speeds execution of ColdFire integer-multiply instructions (MULS and MULU) and provides
additional functionality for multiply-accumulate operations. By executing MULS and MULU in the MAC,
execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early
termination that the OEP normally uses if no MAC hardware is present.
The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed
by the addition or subtraction of the product to or from the value in the accumulator. Optionally, the
product may be shifted left or right by 1 bit before addition or subtraction. Hardware support for saturation
arithmetic can be enabled to minimize software overhead when dealing with potential overflow conditions.
Multiply-accumulate operations support 16- or 32-bit input operands in these formats:
The MAC is optimized for 16-bit multiplications to keep the area consumption low. Two 16-bit operands
produce a 32-bit product. Longword operations are performed by reusing the 16-bit multiplier array at the
expense of a small amount of extra control logic. Again, the product of two 32-bit operands is a 32-bit
result. For longword integer operations, only the least significant 32 bits of the product are calculated. For
fractional operations, the entire 64-bit product is calculated and then truncated or rounded to a 32-bit result
using the round-to-nearest (even) method.
Because the multiplier array is implemented in a three-stage pipeline, MAC instructions have an effective
issue rate of 1 cycle for word operations, 3 cycles for longword integer operations, and 4 cycles for 32-bit
fractional operations.
All arithmetic operations use register-based input operands, and summed values are stored in the
accumulator. Therefore, an additional MOVE instruction is needed to store data in a general-purpose
register.
The need to move large amounts of data presents an obstacle to obtaining high throughput rates in DSP
engines. Existing ColdFire instructions can accommodate these requirements. A MOVEM instruction can
efficiently move large data blocks. The ability to load an operand simultaneously from memory into a
register and execute a MAC instruction makes some DSP operations such as filtering and convolution
more manageable.
The programming model includes a mask register (MASK), which can optionally be used to generate an
operand address during MAC + MOVE instructions. The register application with auto-increment
addressing mode supports efficient implementation of circular data queues for memory operands.
9-6
Accumulator
•
•
•
Field
31–0
Signed integers
Unsigned integers
Signed, fixed-point, fractional numbers
Functional Description
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 1.11
Store 32-bits of the result of the MAC operation.
Table 9-5. ACC Field Descriptions
Description
Freescale Semiconductor