MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 182

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Resets, Interrupts, and General System Control
7.7.6
This high-page register has five write-once bits and one write anytime bit. For the write-once bits, only the
first write after reset is honored. All bits in the register can be read at any time. Any subsequent attempt to
write a write-once bit is ignored to avoid accidental changes to these sensitive settings. SOPT1 must be
written to during the reset initialization program to set the desired controls, even if the desired settings are
the same as the reset settings.
7-16
RESERVED
RESERVED
Field
ILOP
ILAD
POR
COP
LVD
PIN
7
6
5
4
3
2
1
0
System Options 1 (SOPT1) Register
Power-On Reset — Reset was caused by the power-on detection logic. Because the internal supply voltage was
ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset occurred while
the internal supply was below the LVD threshold.
0 Reset not caused by POR.
1 POR caused reset.
External Reset Pin — Reset was caused by an active-low level on the external reset pin.
0 Reset not caused by external reset pin.
1 Reset came from external reset pin.
Computer Operating Properly (COP) Watchdog — Reset was caused by the COP watchdog timer timing out.
This reset source can be blocked by SOPT1[COPT] = 0b00.
0 Reset not caused by COP timeout.
1 Reset caused by COP timeout.
Illegal Opcode — Reset was caused by an attempt to execute an unimplemented or illegal opcode. This includes
any illegal instruction [except the ILLEGAL (0x4AFC) opcode] or a privilege violation (execution of a privileged
instruction in user mode). The STOP instruction is considered illegal if stop is disabled by
((SOPT[STOPE] = 0) && (SOPT[WAITE] = 0)). The HALT instruction is considered illegal if the BDM interface is
disabled by XCSR[ENBDM] = 0.
0 Reset not caused by an illegal opcode.
1 Reset caused by an illegal opcode.
Illegal Address — Reset was caused by the processor's attempted access of an illegal address in the memory
map, an address error, an RTE format error or the fault-on-fault condition. All the illegal address resets are
enabled when CPUCR[ARD] = 0. When CPUCR[ARD] = 1, then the appropriate processor exception is
generated instead of the reset, or if a fault-on-fault condition is reached, the processor simply halts.
0 Reset not caused by an illegal access.
1 Reset caused by an illegal access.
RESERVED
Low Voltage Detect — If the LVD is enabled with LVDRE set, and the supply drops below the LVD trip voltage,
an LVD reset will occur. This bit is also set by POR.
0 Reset not caused by LVD trip or POR.
1 Reset caused by LVD trip or POR.
RESERVED
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 7-9. SRS Bit Field Descriptions
Description
Freescale Semiconductor