MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 579

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
PSTBWA
PSTBST
BFHBR
PSTBH
D1HRL
PSTBR
BDFR
22–21
19–16
Field
15–8
26
25
24
23
20
7
Reserved, must be cleared.
BDM force halt on BDM reset. Determines operation of the device after a BDM reset. This bit is cleared after a
power-on reset and is unaffected by any other reset.
0 The device enters normal operation mode following a BDM reset.
1 The device enters in halt mode following a BDM reset, as if the BKGD pin was held low after a power-on-reset
Note: This bit can only change state if XCSR[ENBDM] = 1 and the flash is unsecure.
Background debug force reset. Forces a BDM reset to the device. This bit always reads as 0 after the reset has
been initiated.
0 No reset initiated.
1 Force a BDM reset.
PST trace buffer halt. Indicates if the processor is halted due to the PST trace buffer being full when recording in
a obtrusive mode.
0 PST trace buffer not full
1 CPU halted due to PST trace buffer being full in obtrusive mode
PST trace buffer state. Indicates the current state of the PST trace buffer recording.
00 PSTB disabled
01 PSTB enabled and waiting for the start condition
10 PSTB enabled, recording and waiting for the stop condition
11 PSTB enabled, completed recording after the stop condition was reached
Reserved, must be cleared.
Debug 1-pin hardware revision level. Indicates the hardware revision level of the 1-pin debug module implemented
in the ColdFire core. For this device, this field is 0x1.
PST trace buffer write address. Indicates the current write address of the PST trace buffer. The most significant
bit of this field is sticky; if set, it remains set until a PST/DDATA reset event occurs. As the ColdFire core inserts
PST and DDATA packets into the trace buffer, this field is incremented. The value of the write address defines the
next location in the PST trace buffer to be loaded. In other words, the contents of PSTB[PSTBWA-1] is the last
valid entry in the trace buffer.
The msb of this field can be used to determine if the entire PST trace buffer has been loaded with valid data.
The PSTBWA is unaffected when a buffer stop condition has been reached, the buffer is disabled, or a system
reset occurs. This allows the contents of the PST trace buffer to be retrieved after these events to assist in debug.
Note: Since this device contains a 64-entry trace buffer, PSTBWA[6] is always zero.
PST trace buffer reset. Generates a reset of the PST trace buffer logic, which clears PSTBWA and PSTBST. The
same resources are reset when a disabled trace buffer becomes enabled and upon the receipt of a BDM GO
command when operating in obtrusive trace mode. These reset events also clear any accumulation of PSTs. This
bit always reads as a zero.
0 Do not force a PST trace buffer reset
1 Force a PST trace buffer reset
or standard BDM-initiated reset.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 26-9. CSR2 Field Descriptions (continued)
PSTBWA[7]
0
1
PSTBWA, PSTBWA+1,..., 0, 1, PSTBWA-1
PSTB Valid Data Locations
Description
(Oldest to Newest)
0, 1, ... PSTBWA-1
Version 1 ColdFire Debug (CF1_DEBUG)
26-15