MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 594

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
communication clock rate determined by the target BDC clock rate. The BDC clock rate may be the system
bus clock frequency or an alternate frequency source depending on the state of XCSR[CLKSW]. All
communication is initiated and controlled by the host which drives a high-to-low edge to signal the
beginning of each bit time. Commands and data are sent most significant bit (msb) first. For a detailed
description of the communications protocol, refer to
Section 26.4.1.3, “BDM Communication
Details”.
If a host is attempting to communicate with a target MCU that has an unknown BDC clock rate, a SYNC
command may be sent to the target MCU to request a timed synchronization response signal from which
the host can determine the correct communication speed. After establishing communications, the host can
read XCSR and write the clock switch (CLKSW) control bit to change the source of the BDC clock for
further serial communications if necessary.
BKGD is a pseudo-open-drain pin and there is an on-chip pullup so no external pullup resistor is required.
Unlike typical open-drain pins, the external RC time constant on this pin, which is influenced by external
capacitance, plays almost no role in signal rise time. The custom protocol provides for brief, actively
driven speed-up pulses to force rapid rise times on this pin without risking harmful drive level conflicts.
Refer to
Section 26.4.1.3, “BDM Communication
Details,”
for more details.
When no debugger pod is connected to the standard 6-pin BDM interface connector
(Section 26.4.4,
“Freescale-Recommended BDM
Pinout”), the internal pullup on BKGD chooses normal operating mode.
When a development system is connected, it can pull BKGD and RESET low, release RESET to select
active background (halt) mode rather than normal operating mode, and then release BKGD. It is not
necessary to reset the target MCU to communicate with it through the background debug interface. There
is also a mechanism to generate a reset event in response to setting CSR2[BDFR].
26.4.1.3
BDM Communication Details
The BDC serial interface requires the external host controller to generate a falling edge on the BKGD pin
to indicate the start of each bit time. The external controller provides this falling edge whether data is
transmitted or received.
BKGD is a pseudo-open-drain pin that can be driven by an external controller or by the MCU. Data is
transferred msb first at 16 BDC clock cycles per bit (nominal speed). The interface times-out if 512 BDC
clock cycles occur between falling edges from the host. If a time-out occurs, the status of any command
in progress must be determined before new commands can be sent from the host. To check the status of
the command, follow the steps detailed in the bit description of XCSR[CSTAT] in
Table
26-7.
The custom serial protocol requires the debug pod to know the target BDC communication clock speed.
The clock switch (CLKSW) control bit in the XCSR[31–24] register allows you to select the BDC clock
source. The BDC clock source can be the bus clock or the alternate BDC clock source. When the MCU is
reset in normal user mode, CLKSW is cleared and that selects the alternate clock source. This clock source
is a fixed frequency independent of the bus frequency so it does change if the user modifies clock generator
settings. This is the preferred clock source for general debugging.
When the MCU is reset in active background (halt) mode, CLKSW is set which selects the bus clock as
the source of the BDC clock. This CLKSW setting is most commonly used during flash memory
programming because the bus clock can usually be configured to operate at the highest allowed bus
frequency to ensure the fastest possible flash programming times. Because the host system is in control of
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
26-30
Freescale Semiconductor