MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 358

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (IIC)
15.4.4.1.2
The IIC shall assume that the bus is idle, when it has determined that the SMBCLK and SMBDAT signals
have been high for at least T
after a STOP condition appears on the bus; 2) HIGH timeout detected after a START condition, but before
a STOP condition appears on the bus.Any master detecting either scenario can assume the bus is free then
SHTF rises. HIGH timeout occurred in scenario 2 if it ever detects that both the following is true:BUSY
bit is high and SHTF is high.
15.4.4.1.3
Figure1-10: Timeout measurement intervals illustrates the definition of the timeout intervals, T
and T
greater than T
ACK-to-STOP. When CSMBCLK TIMEOUT MEXT occurs SMBus MEXT will rise and also trigger the
SLTF.
15.4.4.1.4
A Master is allowed to abort the transaction in progress to any slave that violates the T
T
conclusion of the byte transfer in progress. When slave, the I2C must not cumulatively extend its clock
cycles for a period greater than T
CSMBCLK TIMEOUT SEXT occurs SEXT will rise and also trigger SLTF.
15-20
TIMEOUT,MIN
LOW:MEXT
SCL
SDA
LOW:MEXT
specifications. This can be accomplished by the Master issuing a STOP condition at the
SCL High (SMBus Free) Timeout
CSMBCLK TIMEOUT MEXT
CSMBCLK TIMEOUT SEXT
CSMBCLK TIMEOUT SEXT and MEXT are optional functions which will
be implemented in second step.
. When master mode, the I2C must not cumulatively extend its clock cycles for a period
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Start
T
within a byte, where each byte is defined as START-to-ACK, ACK-to-ACK, or
LOW:MEXT
HIGH:MAX.
Figure 15-15. Timeout measurement intervals
LOW:SEXT
Clk
HIGH timeout can occur in two ways: 1) HIGH timeout detected
Ack
during any message from the initial START to the STOP. When
T
LOW:SEXT
T
LOW:MEXT
NOTE
Clk
Ack
T
LOW:MEXT
Stop
Freescale Semiconductor
LOW:SEXT
LOW:SEXT
or