MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 584

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as
debug control register 0x07 using the WDEBUG instruction and through the BDM port using the
WRITE_DREG command.
26-20
Reset
Reset
L2EBL
31–30
28–22
DRc: 0x07 (TDR)
L2ED
Field
TRC
29
W
W L2T
R
R
31
15
0
0
Trigger response control. Determines how the processor responds to a completed trigger condition. The trigger
response is displayed on PST.
00 Display on PST only
01 Processor halt
10 Debug interrupt
11 Reserved
Enable level 2 breakpoint. Global enable for the breakpoint trigger.
0 Disables all level 2 breakpoints
1 Enables all level 2 breakpoint triggers
Enable level 2 data breakpoint. Setting an L2ED bit enables the corresponding data breakpoint condition based on
the size and placement on the processor’s local data bus. Clearing all ED bits disables data breakpoints.
TRC
L1T L1EBL
30
14
0
0
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
L2EBL
29
13
0
0
TDR Bit
28
12
0
0
28
27
26
25
24
23
22
Figure 26-9. Trigger Definition Register (TDR)
27
11
0
0
Table 26-14. TDR Field Descriptions
Data longword. Entire processor’s local data bus.
Lower data word.
Upper data word.
Lower lower data byte. Low-order byte of the low-order word.
Lower middle data byte. High-order byte of the low-order word.
Upper middle data byte. Low-order byte of the high-order word.
Upper upper data byte. High-order byte of the high-order word.
26
10
0
0
L2ED
L1ED
25
0
9
0
Description
24
0
8
0
Second Level Trigger
First Level Trigger
Description
23
0
0
7
22
0
6
0
L2DI
L1DI
21
0
5
0
20
0
0
4
Access: Supervisor write-only
L2EA
L1EA
19
0
0
Freescale Semiconductor
3
18
0
0
2
BDM write-only
L2EPC L2PCI
L1EPC L1PCI
17
0
0
1
16
0
0
0