MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 464

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Analog-to-Digital Converter (S08ADC16)
21.4.1
This section describes the function of the ADC status and channel control registers, ADCSC1A through
ADCSC1n. ADCSC1A is used for both software and hardware trigger modes of operation.
ADCSC1B-ADCSC1n indicate potentially multiple ADCSC1 registers for use only in hardware trigger
mode. Consult the module introduction for information on the number of ADCSC1n registers specific to
this MCU. The ADCSC1A to ADCSC1n registers have identical fields, and are used in a “ping-pong”
approach to control ADC operation. At any one point in time, only one of the ADCSC1A to ADCSC1n
registers is actively controlling ADC conversions. Updating ADCSC1A while ADCSC1n is actively
controlling a conversion is allowed (and vice-versa for any of the ADCSC1n registers specific to this
MCU). Writing ADCSC1A while ADCSC1A is actively controlling a conversion aborts the current
conversion. In software trigger mode (ADTRG=0), writes to ADCSC1A subsequently initiates a new
conversion (if the ADCHn bits are equal to a value other than all 1s). Similarly, writing any of the
ADCSC1n registers while that specific ADCSC1n register is actively controlling a conversion aborts the
current conversion. Any of the ADCSC1B -ADCSC1n registers are not used for software trigger operation
and therefore writes to the ADCSC1B -ADCSC1n registers do not initiate a new conversion.
21-8
COCOn
AIENn
Field
7
6
Reset:
W
R
Status and Control Registers 1 (ADCSC1A:ADCSC1n)
Conversion Complete Flag - The COCOn flag is a read-only bit that is set each time a conversion is completed
when the compare function is disabled (ACFE=0) and the hardware average function is disabled (AVGE=0).
When the compare function is enabled (ACFE=1), the COCOn flag is set upon completion of a conversion only
if the compare result is true. When the hardware average function is enabled (AVGE=1), the COCOn flag is set
upon completion of the selected number of conversions (determined by the AVGS bits). The COCO1 flag will also
set at the completion of a Calibration sequence. The COCOn bit is cleared when the respective ADCSCn is
written or when the respective ADCRLn is read.
0 Conversion not completed
1 Conversion completed
Interrupt Enable - AIENn enables conversion complete interrupts. When COCOn becomes set while the
respective AIENn is high, an interrupt is asserted.
0 Conversion complete interrupt disabled
1 Conversion complete interrupt enabled
COCOn
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
7
0
Figure 21-2. Status and Channel Control Register 1n (ADCSC1n)
AIENn
Table 21-3. ADCSC1:ADCSC1n Field Descriptions
0
6
DIFFn
0
5
1
4
Description
1
3
ADCHn
1
2
Freescale Semiconductor
1
1
1
0