MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 472

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Analog-to-Digital Converter (S08ADC16)
21.4.8
The ADC Offset Correction Register (ADCOFSH:ADCOFSL) contains the user-selected or
calibration-generated offset error correction value.
This register is a 2’s complement, left justified, 16b value formed by the concatenation of:
The value in the offset correction registers (ADCOFSH:ADCOFSL) is subtracted from the conversion and
the result is transferred into the result registers (ADCRHn:ADCRLn).
If the result is above the maximum or below the minimum result value, it is forced to the appropriate limit
for the current mode of operation.For additional information, please see
21-16
ADCO
AVGE
AVGS
CALF
Field
•
•
CAL
1:0
7
6
3
2
ADCOFSH
ADCOFSL.
ADC Offset Correction Register (ADCOFSH:ADCOFSL)
Calibration - CAL begins the calibration sequence when set. This bit stays set while the calibration is in
progress and is cleared when the calibration sequence is complete. The CALF bit must be checked to
determine the result of the calibration sequence. Once started, the calibration routine cannot be
interrupted by writes to the ADC registers or the results will be invalid and the CALF bit will set. Setting
the CAL bit will abort any current conversion.
Calibration Failed Flag - CALF displays the result of the calibration sequence. The calibration sequence will fail
if ADTRG = 1, any ADC register is written, or any stop mode is entered before the calibration sequence
completes.The CALF bit is cleared by writing a 1 to this bit.
0 Calibration completed normally.
1 Calibration failed. ADC accuracy specifications are not guaranteed.
Continuous Conversion Enable - ADCO enables continuous conversions.Refer to
information on initiating conversions.
0 One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating
1 Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after
Hardware average enable - AVGE enables the hardware average function of the ADC.
0 Hardware average function disabled
1 Hardware average function enabled
Hardware Average select - AVGS determine how many ADC conversions will be averaged to create the ADC
average result.
00 - 4 Samples averaged
01 - 8 Samples averaged
10 - 16 Samples averaged
11 - 32 Samples averaged
a conversion.
initiating a conversion.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Table 21-12. ADCSC3 Register Field Descriptions
NOTE
Description
Section
21.5.8.
Section 21.5.5.1
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