MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 315

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clearing of this interrupts depends on state of SPIxC3[3] and the status of TNEAREF as described
Section 13.3.4, “SPI Status Register
13.4.11.6 RNFULLF
RNFULLF is set when more than three16bit word or six 8bit bytes of data remain in the receive FIFO
provided SPIxC3[4] = 0 or when more than two 16bit word or four 8bit bytes of data remain in the receive
FIFO provided SPIxC3[4] = 1.
Clearing of this interrupts depends on state of SPIxC3[3] and the status of RNFULLF as described
Section 13.3.4, “SPI Status Register
13.5
13.5.1
13.5.1.1
Before the SPI module can be used for communication, an initialization procedure must be carried out, as
follows:
13.5.1.2
In this example, the SPI module will be set up for master mode with only hardware match interrupts
enabled. The SPI will run in 16-bit mode at a maximum baud rate of bus clock divided by 2. Clock phase
and polarity will be set for an active-high SPI clock where the first edge on SPSCK occurs at the start of
the first cycle of a data transfer.
Freescale Semiconductor
1. Update control register 1 (SPIxC1) to enable the SPI and to control interrupt enables. This register
2. Update control register 2 (SPIxC2) to enable additional SPI functions such as the SPI match
3. Update the baud rate register (SPIxBR) to set the prescaler and bit rate divisor for an SPI master.
4. Update the hardware match register (SPIxMH:SPIxML) with the value to be compared to the
5. In the master, read SPIxS while SPTEF = 1, and then write to the transmit data register
also sets the SPI as master or slave, determines clock phase and polarity, and configures the main
SPI options.
interrupt feature, the master mode-fault function, and bidirectional mode output. 8- or 16-bit mode
select and other optional features are controlled here as well.
receive data register for triggering an interrupt if hardware match interrupts are enabled.
(SPIxDH:SPIxDL) to begin transfer.
Initialization/Application Information
SPI Module Initialization Example
Initialization Sequence
Pseudo—Code Example
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
(SPIxS).”
(SPIxS).”
16-Bit Serial Peripheral Interface (SPI16)
13-29