MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 568

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Active background
Version 1 ColdFire Debug (CF1_DEBUG)
to clear security, which involves mass erasing the on-chip flash memory. No other debug access is allowed.
Secure mode can be used in conjunction with each of the wait and stop low-power modes.
If the BDM interface is not enabled, access to the debug resources is limited in the same manner as a secure
device.
If the device is not secure and the BDM interface is enabled (XCSR[ENBDM] is set), the device is
operating in debug mode and additional resources are available via the BDM interface. In this mode, the
status of the processor (running, stopped, or halted) determines which BDM commands may be used.
Debug mode functions are managed through the background debug controller (BDC) in the Version 1
ColdFire core. The BDC provides the means for analyzing MCU operation during software development.
BDM commands can be classified into three types as shown in
For more information on these three BDM command classifications, see
Command Set Summary.”
The core’s halt mode is entered in a number of ways:
26-4
Command Type
Always-available
Non-intrusive
•
•
•
•
•
•
•
•
•
•
The BKGD pin is low during POR
The BKGD pin is low immediately after a BDM-initiated force reset (see CSR2[BDFR] in
Section 26.3.3, “Configuration/Status Register 2 (CSR2),”
A background debug force reset occurs (CSR2[BDFR] is set) and CSR2[BFHBR] is set
A computer operating properly reset occurs and CSR2[COPHR] is set
An illegal operand reset occurs and CSR2[IOPHR] is set
An illegal address reset occurs and CSR2[IADHR] is set
A BACKGROUND command is received through the BKGD pin. If necessary, this wakes the
device from STOP/WAIT modes.
A properly-enabled (XCSR[ENBDM] is set) HALT instruction is executed
Encountering a BDM breakpoint and the trigger response is programmed to generate a halt
Reaching a PSTB trace buffer full condition when operating in an obtrusive recording mode
(CSR2[PSTBRM] is set to 01 or 11)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Secure or
Unsecure
Unsecure
Unsecure
Secure?
Flash
Enabled or
Disabled
Enabled
Enabled
BDM?
Table 26-2. BDM Command Types
Core Status
Run, Halt
Halt
—
• Read/write access to XCSR[31–24], CSR2[31–24],
• Memory access
• Memory access with status
• Debug register access
• BACKGROUND
• Read or write CPU registers (also available in stop mode)
• Single-step the application
• Exit halt mode to return to the application program (GO)
CSR3[31–24]
Table
for details)
26-2.
Section 26.4.1.5, “BDM
Command Set
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