MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 169

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The write to SRS that services (clears) the COP counter should not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
If the bus clock source is selected, the COP counter does not increment while the microcontroller is in
background debug mode or while the system is in stop mode. The COP counter resumes when the
microcontroller exits background debug mode or stop mode.
If the 1 kHz clock source is selected, the COP counter is re-initialized to zero upon entry to either
background debug mode or stop mode and begins from zero upon exit from background debug mode or
stop mode.
7.3.3
The default configuration of the V1 ColdFire core enables the generation of an MCU reset in response to
the processor's attempted execution of an illegal instruction (except for the ILLEGAL opcode), illegal line
A, illegal line F instruction or the detection of a privilege violation (attempted execution of a supervisor
instruction while in user mode).
The attempted execution of the STOP instruction with (SOPT[STOPE] = 0 && SOPT[WAITE] = 0) is
treated as an illegal instruction.
The attempted execution of the HALT instruction with XCSR[ENBDM] = 0 is treated as an illegal
instruction.
The processor generates a reset in response to any of these events if CPUCR[IRD] = 0. If this
configuration bit is set, the processor generates the appropriate exception instead of forcing a reset.
7.3.4
The default configuration of the V1 ColdFire core enables the generation of an MCU reset in response to
any processor-detected address error, bus error termination, RTE format error or fault-on-fault condition.
The processor generates a reset if CPUCR[ARD] = 0. If this configuration bit is set, the processor
generates the appropriate exception instead of forcing a reset, or simply halts the processor in response to
the fault-on-fault condition.
7.4
The interrupt architecture of ColdFire utilizes a 3-bit encoded interrupt priority level sent from the
interrupt controller to the core, providing 7 levels of interrupt requests. Level 7 represents the highest
priority interrupt level, while level 1 is the lowest priority. The processor samples for active interrupt
requests once per instruction by comparing the encoded priority level against a 3-bit interrupt mask
value (I) contained in bits 10:8 of the processor’s status register (SR). If the priority level is greater than
the SR[I] field at the sample point, the processor suspends normal instruction execution and initiates
interrupt exception processing.
Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6
are treated as level-sensitive and may be masked depending on the value of the SR[I] field. For correct
Freescale Semiconductor
Interrupts & Exceptions
Illegal Opcode Detect (ILOP)
Illegal Address Detect (ILAD)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Resets, Interrupts, and General System Control
7-3