MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 170

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Resets, Interrupts, and General System Control
operation, the ColdFire processor requires that, once asserted, the interrupt source remain asserted until
explicitly disabled by the interrupt service routine.
During the interrupt exception processing, the CPU does the following tasks in order:
This byte-sized operand fetch during exception processing is known as the interrupt acknowledge (IACK)
cycle. The fetched data provides an index into the exception vector table which contains up to 256
addresses (depending upon the specific device), each pointing to the beginning of a specific exception
service routine.
In particular, the first 64 exception vectors are reserved for the processor to handle reset, error conditions
(access, address), arithmetic faults, system calls, etc. Vectors 64–255 are reserved for interrupt service
routines. The MCF51EM series microcontrollers support 36 peripheral interrupt sources and an additional
seven software interrupt sources. These are mapped into the standard seven ColdFire interrupt levels, with
up to 9 levels of prioritization within a given level by the V1 ColdFire interrupt controller. See
for details.
Once the interrupt vector number has been retrieved, the processor continues by creating a stack frame in
memory. For ColdFire, all exception stack frames are two longwords in length, and contain 32 bits of
vector and status register data, along with the 32-bit program counter value of the instruction that was
interrupted. After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer
from the exception vector table using the vector number as the offset, and then jumps to that address to
begin execution of the service routine. After the status register is stored in the exception stack frame, the
SR[I] mask field is set to the level of the interrupt being acknowledged, effectively masking that level and
all lower values while in the service routine.
All ColdFire processors guarantee that the first instruction of the service routine is executed before
interrupt sampling is resumed. By making this initial instruction a write to the SR, interrupts can be safely
disabled, if required. Optionally, the processor can be configured to automatically raise the mask level to
7 for any interrupt during exception processing by setting CPUCR[IME] = 1.
During the execution of the service routine, the appropriate actions must be performed on the peripheral
to negate the interrupt request.
For more information on exception processing, see the ColdFire Programmer’s Reference Manual. For
additional information specific to this device, see
7.4.1
External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events.
7-4
1. Enter supervisor mode,
2. Disable trace mode,
3. Use the vector provided by the INTC when the interrupt was signaled (if CPUCR[IACK] = 0) or
explicitly fetches an 8-bit vector from the INTC (if CPUCR[IACK] = 1).
External Interrupt Request (IRQ) Pin
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Chapter 10, “Interrupt Controller
(CF1_INTC).”
Freescale Semiconductor
Table 7-1