MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 162

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Modes of Operation
In addition to the above, upon waking up from stop2, SPMSC2[PPDF] is set. This flag is used to direct
user code to go to a stop2 recovery routine. PPDF remains set and the I/O pin states remain latched until
a 1 is written to SPMSC2[PPDACK].
Wakeup from stop2 can be initiated with an IRTC interrupt. Unlike most other modules on the chip, the
IRTC is not reset as a result of exiting stop2. This implies that the IRTC interrupt is asserted (although
masked) upon exit from stop2.
To maintain I/O states for pins configured as general-purpose I/O before entering stop2, restore the
contents of the I/O port registers, which have been saved in RAM, to the port registers before writing to
the PPDACK bit. If the port registers are not restored from RAM before writing to PPDACK, the pins
switch to their reset states when PPDACK is written.
For pins that were configured as peripheral I/O, reconfigure the peripheral module that interfaces to the
pin before writing to PPDACK. If the peripheral module is not enabled before writing to PPDACK, the
pins are controlled by their associated port control registers when the I/O latches are opened.
6.8.1.1
If using a low-range oscillator during stop2, reconfigure the ICSC2 register before PPDACK is written.
The low-range oscillator (ICSC2[RANGE] = 0) can operate in stop2 as the clock source for the LCD
module. If the low-range oscillator is active when entering stop2, it remains active in stop2 regardless of
the value of ICSC2[EREFSTEN]. To disable the oscillator in stop2, switch the ICS into FBI or FEI mode
before executing the STOP instruction.
The crystal oscillator cannot be used in high range in stop2. Systems which utilize crystals in the high
frequency range (up to 25MHz) must disable the crystal oscillator and switch to FBI or FEI mode prior to
executing the STOP instruction.
6.8.2
Stop3 mode is entered by executing a STOP instruction under the conditions as shown in
states of all of the internal registers and logic, RAM contents, and I/O pin states are maintained. The
on-chip regulator is placed in standby state.
Stop3 can be exited by asserting RESET or by an interrupt from one of the following sources: the
PRACMP, IRTC, ADC, IRQ, SCI, LCD or KBI. The following modules are inactive in stop3: SPI, IIC,
MTIM, MTIM16, PDB and TPM
If stop3 is exited by the RESET pin, the MCU is reset and operation resumes after taking the reset vector.
Exit by one of the internal interrupt sources results in the MCU taking the appropriate interrupt vector.
6-10
•
•
The LVD reset function is enabled and the MCU remains in the reset state if V
trip point (low trip point selected due to POR).
The CPU initiates reset exception processing by fetching the vectors at 0x(00)00_0000 and
0x(00)00_0004.
Stop3 Mode
XOSC2 Considerations for Stop2
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Freescale Semiconductor
DD
is below the LVD
Table
6-1. The