MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 108

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Memory
3.6
Several reserved flash memory locations, shown in
corresponding peripheral registers. These registers include an 8-byte backdoor key which can be used to
3-52
Figure 3-16. Procedure for Clearing Security on MCF51EM256 Series MCUs via the BDM Port 2
write xcsr[31:24]=0x97 to transfer PTIMER info to
write xcsr[31:24]=0x97 to transfer PTIMER info to
hold BKGD=0, apply power, wait N+16 cycles for
hold BKGD=0, apply power, wait N+16 cycles for
secure state unknown,, CPU halted, FEI 10MHz
secure state unknown,, CPU halted, FEI 10MHz
write xcsr[31:24]=0x8F to transfer divider info to
write xcsr[31:24]=0x8F to transfer divider info to
Flash Module Reserved Memory Locations
secure state unknown, CPU halted, FEI 10MHz
secure state unknown, CPU halted, FEI 10MHz
FTSR and initiate erase/verify of flash memory
FTSR and initiate erase/verify of flash memory
set PRDIV8 and clock divider fields in CSR3
set PRDIV8 and clock divider fields in CSR3
secure state unknown / unpowered
secure state unknown / unpowered
clock, synchronized to debugger
clock, synchronized to debugger
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Write PTIMER bits to CSR3
Write PTIMER bits to CSR3
clock, sync required
clock, sync required
POR to de-assert
POR to de-assert
Read XCSR
Read XCSR
SYNC
SYNC
FTSR
FTSR
A
A
xcsr[31:24]==0x87
xcsr[31:24]==0x87
Table
xcsr[25]=0
xcsr[25]=0
3-15, are used for storing values used by
N = number of cycles for SIM to release
N = number of cycles for SIM to release
internal reset. Adder of 16 imposed by the
internal reset. Adder of 16 imposed by the
ColdFire core.
ColdFire core.
BKGD=0 during reset will
BKGD=0 during reset will
ensure that ENBDM comes up "1"
ensure that ENBDM comes up "1"
FLL Enabled, Internal Reference (FEI)
FLL Enabled, Internal Reference (FEI)
at 10MHz is reset default for the ICS
at 10MHz is reset default for the ICS
xcsr[31:24] != 1000 01-1
xcsr[31:24] != 1000 01-1
STOP
STOP
STOP
STOP
error condition
error condition
check code or device
check code or device
already unsecured
already unsecured
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