MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 356

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (IIC)
15.4.2
For 10-bit addressing, bit 11110 is used for the first 5 bits of the first address byte. Various combinations
of read/write formats are possible within a transfer that includes 10-bit addressing.
15.4.2.1
The transfer direction is not changed (see
each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own
address and tests whether the eighth bit (R/W direction bit) is 0. It is possible that more than one device
will find a match and generate an acknowledge (A1). Each slave that finds a match will compare the eight
bits of the second byte of the slave address with its own address, but only one slave will find a match and
generate an acknowledge (A2). The matching slave will remain addressed by the master until it receives a
STOP condition (P) or a repeated START condition (Sr) followed by a different slave address.
After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver will see an IIC
interrupt. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated
as valid data.
15.4.2.2
The transfer direction is changed after the second R/W bit (see
acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a
slave-receiver. After the repeated START condition (Sr), a matching slave remembers that it was addressed
before. This slave then checks whether the first seven bits of the first byte of the slave address following
Sr are the same as they were after the START condition (S), and tests whether the eighth (R/W) bit is 1. If
there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge
A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or a repeated START
condition (Sr) followed by a different slave address.
After a repeated START condition (Sr), all other slave devices will also compare the first seven bits of the
first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of
them will be addressed because R/W = 1 (for 10-bit devices), or the 11110XX slave address (for 7-bit
devices) does not match.
After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter will see an IIC
interrupt. User software must ensure that for this interrupt, the contents of IICD are ignored and not treated
as valid data.
15-18
S
11110 + AD10 + AD9
Slave Address
1st 7 bits
S
Table 15-15. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address
10-Bit Address
Table 15-14. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address
Slave Address 1st 7 bits
Master-Transmitter Addresses a Slave-Receiver
Master-Receiver Addresses a Slave-Transmitter
11110 + AD10 + AD9
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
R/W
0
A1
Slave Address
R/W
2nd byte
AD[8:1]
0
A1
Table
Slave Address 2nd byte
A2
15-14). When a 10-bit address follows a START condition,
Sr
AD[8:1]
11110 + AD10 + AD9
Slave Address
1st 7 bits
Table
A2
Data
15-15). Up to and including
R/W
1
A
A3
...
Data
Data
Freescale Semiconductor
A
A/A
...
Data
P
A
P