MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 617

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Unlike a normal bit transfer, where the host initiates the transmission by issuing a negative edge in the
BKGD pin, the serial interface ACK handshake pulse is initiated by the target MCU. The hardware
handshake protocol in
should follow these timing relationships to avoid the risks of an electrical conflict at the BKGD pin.
The ACK handshake protocol does not support nested ACK pulses. If a BDC command is not
acknowledged by an ACK pulse, the host first needs to abort the pending command before issuing a new
BDC command. When the CPU enters a stop mode at about the same time the host issues a command that
requires CPU execution, the target discards the incoming command. Therefore, the command is not
acknowledged by the target, meaning that the ACK pulse is not issued in this case. After a certain time,
the host could decide to abort the ACK protocol to allow a new command. Therefore, the protocol provides
a mechanism where a command (a pending ACK) could be aborted. Unlike a regular BDC command, the
ACK pulse does not provide a timeout. In the case of a STOP instruction where the ACK is prevented from
being issued, it would remain pending indefinitely if not aborted. See the handshake abort procedure
described in
26.4.1.7
The abort procedure is based on the SYNC command. To abort a command that has not responded with an
ACK pulse, the host controller generates a sync request (by driving BKGD low for at least 128 serial clock
cycles and then driving it high for one serial clock cycle as a speedup pulse). By detecting this long low
pulse on the BKGD pin, the target executes the sync protocol (see
assumes that the pending command and therefore the related ACK pulse, are being aborted. Therefore,
after the sync protocol completes, the host is free to issue new BDC commands.
Because the host knows the target BDC clock frequency, the SYNC command does not need to consider
the lowest possible target frequency. In this case, the host could issue a SYNC close to the 128 serial clock
cycles length, providing a small overhead on the pulse length to assure the sync pulse is not misinterpreted
by the target.
It is important to notice that any issued BDC command that requires CPU execution is scheduled for
execution by the pipeline based on the dynamic state of the machine, provided the processor does not enter
any of the stop modes. If the host aborts a command by sending the sync pulse, it should then read
XCSR[CSTAT] after the sync response is issued by the target, checking for CSTAT cleared, before
Freescale Semiconductor
BKGD PIN
Section 26.4.1.7, “Hardware Handshake Abort Procedure.”
Hardware Handshake Abort Procedure
READ_MEM.B
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 26-21
HOST
Figure 26-21. Handshake Protocol at Command Level
ADDRESS[23–0]
TARGET
DEBUG DECODES
THE COMMAND
specifies the timing when the BKGD pin is being driven, so the host
CPU EXECUTES THE
COMMAND
READ_MEM.B
TARGET
Section 26.4.1.5.1,
RETRIEVED
BDC ISSUES THE
ACK PULSE (NOT TO SCALE)
BYTE IS
HOST
Version 1 ColdFire Debug (CF1_DEBUG)
NEW BDC COMMAND
HOST
“SYNC”), and
TARGET
26-53