MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 293

IC MCU 32BIT 256KB FLASH 100LQFP

MCF51EM256CLL

Manufacturer Part Number
MCF51EM256CLL
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Freescale Semiconductor
Series
MCF51EMr
Datasheets

Specifications of MCF51EM256CLL

Core Processor
Coldfire V1
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SCI, SPI
Peripherals
LCD, LVD, PWM, WDT
Number Of I /o
63
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Processor Series
MCF51EM
Core
ColdFire V1
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
RS-232, LIN
Maximum Clock Frequency
50 MHz
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
DEMOEM
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
MCF51EM256CLL
Manufacturer:
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Quantity:
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Part Number:
MCF51EM256CLL
Manufacturer:
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Quantity:
10 000
13.3.2
This read/write register is used to control optional features of the SPI system. Bits 6 and 5 are not
implemented and always read 0.
Freescale Semiconductor
SPIMODE
Reset
LSBFE
SPMIE
SSOE
Field
Field
1
0
7
6
W
R
SPMIE
SPI Control Register 2 (SPIxC2)
Slave Select Output Enable — This bit is used in combination with the mode fault enable (MODFEN) bit in
SPIxC2 and the master/slave (MSTR) control bit to determine the function of the SS pin as shown in
LSB First (Shifter Direction) — This bit does not affect the position of the MSB and LSB in the data register.
Reads and writes of the data register always have the MSB in bit 7 (or bit 15 in 16-bit mode).
0 SPI serial data transfers start with most significant bit
1 SPI serial data transfers start with least significant bit
SPI Match Interrupt Enable — This is the interrupt enable for the SPI receive data buffer hardware match
(SPMF) function.
0 Interrupts from SPMF inhibited (use polling).
1 When SPMF = 1, requests a hardware interrupt.
SPI 8- or 16-bit Mode — This bit allows the user to select either an 8-bit or 16-bit SPI data transmission length.
In master mode, a change of this bit will abort a transmission in progress, force the SPI system into idle state,
and reset all status bits in the SPIxS register. Refer to section
0 8-bit SPI shift register, match register, and buffers.
1 16-bit SPI shift register, match register, and buffers.
0
7
MODFEN
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
0
0
1
1
= Unimplemented or Reserved
SPIMODE
0
6
Table 13-1. SPIxC1 Field Descriptions (continued)
SSOE
Table 13-3. SPIxC2 Register Field Descriptions
Figure 13-4. SPI Control Register 2 (SPIxC2)
0
1
0
1
0
0
5
Table 13-2. SS Pin Function
General-purpose I/O (not SPI)
General-purpose I/O (not SPI)
SS input for mode fault
Automatic SS output
MODFEN
Master Mode
0
4
Description
Description
BIDIROE
3
0
Section 13.4.4, “SPI FIFO
Slave select input
Slave select input
Slave select input
Slave select input
16-Bit Serial Peripheral Interface (SPI16)
0
0
2
Slave Mode
SPISWAI
MODE,” for details.
0
1
Table
SPC0
0
0
13-2.
13-7

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