MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 528

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LCD Driver Module
Read: anytime
Write: anytime
24.3.8
When LCDPEN[n] = 1, these bits configure the corresponding LCD pin to operate as an LCD backplane
or an LCD frontplane. Most applications set a maximum of eight of these bits. Initialize these registers
before enabling the LCD module. Exiting stop2 mode does not require reinitializing the LCDBPEN
registers.
These registers should only be written with instructions that perform byte writes, using instructions that
perform word writes will lead to invalid data being placed in the register.
24-12
LCDPEN0
LCDPEN1
LCDPEN2
LCDPEN3
LCDPEN4
LCDPEN5
PEN[43:0]
Field
Backplane Enable Registers 0–7 (BPEN0–BPEN7)
Reset
Reset
Reset
Reset
Reset
Reset
LCD Pin Enable — The PEN[43:0] bit enables the LCD[43:0] pin for LCD operation. Each LCD[43:0] pin can be
configured as a backplane or a frontplane based on the corresponding BPEN[n] bit in the Backplane Enable
Register (LCDBPEN[7:0]). If LCDEN = 0, these bits have no effect on the state of the I/O pins. Set PEN[63:0]
bits before LCDEN is set.
0 LCD operation disabled on LCDnn.
1 LCD operation enabled on LCDnn.
W
W
W
W
W
W
R
R
R
R
R
R
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Figure 24-8. LCD Pin Enable Registers 0–7 (LCDPEN0–LCDPEN7)
PEN15
PEN23
PEN31
PEN39
PEN7
7
Table 24-11. LCDPEN0–LCDPEN7 Field Descriptions
PEN14
PEN22
PEN30
PEN38
PEN6
Unimplemented or Reserved
6
PEN13
PEN21
PEN29
PEN37
PEN5
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Description
PEN12
PEN20
PEN28
PEN36
PEN4
4
PEN11
PEN19
PEN27
PEN35
PEN43
PEN3
3
PEN10
PEN18
PEN26
PEN34
PEN42
PEN2
2
Freescale Semiconductor
PEN17
PEN25
PEN33
PEN41
PEN1
PEN9
1
PEN16
PEN24
PEN32
PEN40
PEN0
PEN8
0