MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 156

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Modes of Operation
Figure 6-2
RESET must be asserted low, or the IRTC must issue a wakeup signal, in order to exit stop2. Only interrupt
assertion is necessary to exit the other stop and wait modes.
Figure 6-3
for development purposes. If BDM is enabled, the chip automatically shifts LP modes into their fully
regulated equivalents. If software or debugger sets SPMSC2[LPR] while BDM is enabled,
SPMSC2[LPRS] reflects the fact that the regulator is not in standby. Similarly, SPMSC2[PPDF] does not
indicate a recovery from stop2 if XCSR[ENBDM] forced stop4 to occur in its place.
Stated another way, if XCSR[ENBDM] has been set via the BDM interface, then the power management
controller keeps (or puts) the regulator in full regulation despite other settings on the contrary. The states
shown in
From a software perspective (and disregarding PMC status bits), the system remains in the appropriate
low-power state, and can be debugged as such.
See
1. This can have subtle impacts on recovery from stop. The IRQ input can wake the device from stop4 if it has been enabled for
that purpose. A low on the RESETB pin wakes the device from stop2 (there is an asynchronous path to the power management
controller in that state).
6-4
•
•
•
•
Section 6.7, “Wait Modes,”
LPrun ⇒ Run
LPwait ⇒ Wait
Stop3 ⇒ Stop4
Stop2 ⇒ Stop4
Figure 6-3
Figure 6-2. Allowable Power Mode Transitions for Mission Mode MCF51EM256 Series
Stop4
illustrates mission mode state transitions allowed between the legal states shown in
takes the same set of states and transitions shown in
Wait
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Run
then map as follows:
for a description of the various ways to enter halt mode.
LPwait
Stop3
Stop2
LPrun
Figure 6-2
LPwait
Mode
LPrun
Stop4
Stop3
Stop2
Wait
Run
and adds the BDM halt mode
Regulator State
Partial Power Off
Freescale Semiconductor
Standby
Standby
Standby
Full On
Full On
Full On
1
Table
6-1.