MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 173

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
ADC1_COCO
ADC2_COCO
ADC3_COCO
ADC4_COCO
CMP1_CMP
CMP2_CMP
MTIM1_ovfl
MTIM2_ovfl
MTIM3_ovfl
FTSR1_int
FTSR2_int
TPM_TOF
PDB_ERR
IRTC_INT
LCD_LCD
TPM_ch0
TPM_ch1
Interrupt
FTSR_emptybuf FTSR_FCNFG[CBEIE]
SPI3_int
IIC_int
PDB
FTSR_coco
Interrupt
Table 7-1. MCF51EM256 Series Exception and Interrupt Vector Table (continued)
FTSR1_FCNFG[CBEIE,
FTSR2_FCNFG[CBEIE,
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
LCD_LCDC1[LCDIEN]
TPM_C0SC[CH0IE]
TPM_C1SC[CH1IE]
CMP1_CS[ACIEN]
CMP2_CS[ACIEN]
ADC1_SC1[AIEN]
ADC2_SC1[AIEN]
ADC3_SC1[AIEN]
ADC4_SC1[AIEN]
SPI3_C1[SPTIE]
SPI3_C1[SPIE]
TPM_SC[TOIE]
IRTC_IRTCIER
IIC_CR1[IICIE]
FTSR_FCNFG[CCIE]
Local Enable
FTSR_Local Enable
MTIM1_TOIE
MTIM2_TOIE
MTIM3_TOIE
PDBSC[IE]
CCIE]
CCIE]
N/A
Table 7-2. Unsupported FTSR Interrupts
FTSR1_FSTAT[FCBEF,
FTSR2_FSTAT[FCBEF,
CMP1_CS[ACMPF]
CMP2_CS[ACMPF]
PDBCHnCR[ERRA,
ADC1_SC1[COCO]
ADC2_SC1[COCO]
ADC3_SC1[COCO]
ADC4_SC1[COCO]
LCD_LCDS[LCDIF]
TPM_C0SC[CH0F]
TPM_C1SC[CH1F]
FTSR_FSTAT[FCBEF]
FTSR_FSTAT[FCCF]
SPI3_S[SPTEF]
SPI3_S[MODF]
IRTC_IRTCISR
SPI3_S[SPRF]
TPM_SC[TOF]
IIC_SR[IICIF]
MTIM1_TOF
MTIM2_TOF
MTIM3_TOF
FTSR_Source
PDBSC[IF]
Source
ERRB]
FCCF]
FCCF]
Mode Fault Interrupt
Receive Buffer Full Interrupt
Transmit Buffer Empty Interrrupt
Complete 1-byte tranfer (TCF) Interrupt
Match of received calling address (IAAS) Interrupt
Arbitration Lost (ARBL) Interrupt
SMBus Timeout (SLTF) Interrupt
Conversion Complete Flag
Conversion Complete Flag
Conversion Complete Flag
Conversion Complete Flag
Comparator Interrupt
Comparator Interrupt
MTIM8 Overflow Interrupt
MTIM8 Overflow Interrupt
MTIM8 Overflow Interrupt
Counter Overflow
An input capture or output compare event took
place on channel 0
An input capture or output compare event took
place on channel 1
composite irtc interrupt
LCD Interrupt
composite FTSR interrupt
composite FTSR interrupt
PDB Interrupt
PDB sequence error interrupt (always enabled)
Flash Command Buffer Empty Interrupt
Flash Command Complete Interrupt
Resets, Interrupts, and General System Control
Description
Description
7-7