MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 115

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Refer to tables in
refers to registers and control bits only by their names.
4.2.2.1
An internal pullup device can be enabled for each port pin by setting the corresponding bit in the pullup
enable register (PTxPE[n]). The pullup device is disabled if the pin is either:
4.2.2.2
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTxSE[n]). When enabled, slew control limits the rate at which an output can transition in order
to reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs.
Freescale Semiconductor
Reset:
PTxPEn
•
•
•
•
Field
7–0
W
R
Configured as an output by the parallel I/O control logic
Configured as a shared peripheral function
Controlled by an analog function.
At reset, except for RESETB and BKGD/MS.
PTxPE7
Internal Pull Enable for Port x Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTx pin. For Port x pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pullup device disabled for Port x bit n.
1 Internal pullup device enabled for Port x bit n.
Port x Pull Enable Register (PTxPE)
0
Port x Slew Rate Enable Register (PTxSE)
7
A Freescale Semiconductor-provided equate or header file normally is used
to translate these names into the appropriate absolute addresses.
Register
PTxIFE
PTxDS
PTxPE
PTxSE
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Chapter 3,
PTxPE6
Figure 4-2. Internal Pull Enable for Port x Register (PTxPE)
0
6
“Memory,” for the absolute address assignments for all registers. This section
Table 4-7. PTxPE Field Descriptions
PTxPE5
Table 4-6. Register Set Summary
Port x Drive Strength Selection Register
0
5
Port x Input Filter Enable Register
Port x Slew Rate Enable Register
Port x Pull Enable Register
PTxPE4
Description
NOTE
0
4
Description
PTxPE3
3
0
PTxPE2
2
0
read/write
read/write
read/write
read/write
Access
PTxPE1
0
1
PTxPE0
0
0
4-5