MCF51EM256CLL Freescale Semiconductor, MCF51EM256CLL Datasheet - Page 184

• Manufacturer Part Number: MCF51EM256CLL
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM256CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: DEMOEM
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Resets, Interrupts, and General System Control
7.7.7
This register contains bits that control the PMC LVD trim. This is a reserved register and can not be written
by application code during normal operation.
7.7.8
These high-page read-only registers are included so host development systems can identify the ColdFire
derivative. This allows the development software to recognize where specific memory blocks, registers,
and control bits are located in a target microcontroller.
Additional configuration information about the ColdFire core and memory system is loaded into the 32-bit
D0 (core) and D1 (memory) registers at reset. This information can be stored into memory by the system
startup code for later use by configuration-sensitive application code. See
Exception” for more information.
7-18
1
2
Reset:
PMC_LVD_TRIM
Reset:
Windowed COP operation requires the user to clear the COP timer in the last 25% of the selected timeout period. This column
displays the minimum number of clock counts required before the COP timer can be reset when in windowed COP mode
(SOPT1[COPW] = 1).
Values shown in milliseconds based on t
W
W
R
R
Field
7–5
4–0
System Options 2 Register (SOPT2)
System Device Identification Register (SDIDH, SDIDL)
—
0
0
7
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Reserved, should be cleared.
PMC LVD TRIM. Reserved, Application code must not write these bits.
Figure 7-8. System Device Identification Register — High (SDIDH)
—
0
0
6
6
Figure 7-7. System Options 2 Register (SOPT2)
REV
Table 7-12. SOPT2 Bit Field Descriptions
LPO
—
0
0
5
5
= 1 ms.
—
—
4
4
Description
ID11
—
3
3
1
PMC_LVD_TRIM
ID10
Section 8.3.3.14, “Reset
—
1
2
2
Freescale Semiconductor
ID9
—
0
1
1
ID8
—
0
0
0